Shallow trench isolation structure for strained Si on SiGe

Abstract

A structure, and a method for fabricating the structure, for the isolation of electronic devices is disclosed. The electronic devices are processed in substrates comprising a SiGe based layer underneath a strained Si layer. The isolation structure comprises a trench extending downward from the substrate top surface and penetrating into the SiGe based layer, forming a sidewall in the substrate. An epitaxial Si liner is selectively deposited onto the trench sidewall, and subsequently thermally oxidized. The trench is filled with a trench dielectric, which protrudes above the substrate top surface.

We claim:  
     
         1 . A device structure, comprising: 
 a substrate comprising a Siege based layer, said substrate having a top surface;    a trench extending downward from said top surface penetrating into said Siege based layer, wherein said trench having a sidewall formed in said substrate;    a Si liner covering said sidewall, wherein said Si liner covers a surface of said Siege based layer on said sidewall, and wherein said Si liner is a monocrystalline material in an epitaxial relationship with said sidewall;    an insulator layer grown on said Si liner; and    a trench dielectric, said trench dielectric filling said trench and protruding out of said trench to above said top surface.    
     
     
         2 . The structure of  claim 1 , wherein said substrate comprises a Si layer on top of said Siege based layer.  
     
     
         3 . The structure of  claim 2 , wherein said Si layer is between about 1nm and 50nm thick.  
     
     
         4 . The structure of  claim 3 , wherein said Si layer is tensilely strained.  
     
     
         5 . The structure of  claim 3 , wherein said Siege based layer is between about 5 nm and 5 μm thick.  
     
     
         6 . The structure of  claim 5 , wherein said substrate comprises a buried insulator layer underneath said Siege based layer.  
     
     
         7 . The structure of  claim 6 , wherein said buried insulator layer consists essentially of SiO 2 .  
     
     
         8 . The structure of  claim 1 , wherein said Si liner is between about 1 nm and 50 nm thick.  
     
     
         9 . The structure of  claim 1 , wherein said insulator layer grown on said Si liner consists essentially of SiO 2 .  
     
     
         10 . The structure of  claim 1 , wherein said insulator layer grown on said Si liner consists essentially of silicon-oxynitride.  
     
     
         11 . The structure of  claim 1 , wherein said insulator layer grown on said Si liner is between about 1 nm and 100 nm thick.  
     
     
         12 . The structure of  claim 1 , wherein said trench dielectric protrudes above said top surface by between about 1 nm and 500 nm.  
     
     
         13 . The structure of  claim 1 , wherein said trench dielectric consists essentially of SiO 2 .  
     
     
         14 . The structure of  claim 1 , wherein said trench having a sidewall edge formed where said sidewall intersects said top surface, and wherein said Si liner leaves uncovered a strip shaped surface on said sidewall, wherein said strip shaped surface runs along said sidewall edge.  
     
     
         15 . The structure of  claim 14 , wherein said strip shaped surface is between about 1 nm and 50 nm wide.  
     
     
         16 . A plurality of MOSFET devices fabricated on a top surface of a Substrate, wherein said top surface belongs to a tensilely strained Si layer, wherein said Si layer is in an epitaxial relationship with an underlying Siege based layer, and wherein said plurality of MOSFET devices comprise an isolation structure, said isolation structure comprising: 
 a trench extending downward from said top surface penetrating into said Siege based layer, wherein said trench having a sidewall formed in said substrate;    a Si liner covering said sidewall, wherein said Si liner covers a surface of said Siege based layer on said sidewall, and wherein said Si liner is a monocrystalline material in an epitaxial relationship with said sidewall;    an insulator layer grown on said Si liner; and    a trench dielectric, said trench dielectric filling said trench and protruding out of said trench to above said top surface.    
     
     
         17 . The plurality of MOSFET devices of  claim 16 , wherein a portion of said MOSFET devices are wired into CMOS circuits.  
     
     
         18 . The plurality of MOSFET devices of  claim 17 , wherein said CMOS circuits form logic circuits for a digital processor.  
     
     
         19 . A method for making a device structure, comprising the steps of: 
 taking a substrate comprising a Siege based layer, said substrate having a top surface;    overlaying said substrate with a capping dielectric layer;    etching a trench, wherein said trench cutting through said capping dielectric layer and extending downward from said top surface and penetrating into said Siege based layer, and wherein said trench having an auxiliary sidewall formed in said capping dielectric layer and having a sidewall formed in said substrate;    depositing by selective epitaxy a monocrystalline Si liner over said sidewall including a surface of said Siege based layer on said sidewall, and leaving said auxiliary sidewall void of said Si liner.    
     
     
         20 . The method for making a device structure of  claim 19 , further comprising the steps of: 
 partially consuming said Si liner by growing an insulator on said Si liner;    filling said trench with a trench dielectric to a protruded level which is above said top surface; and    removing said capping dielectric, whereby said trench dielectric is protruding out of said trench to above said top surface.    
     
     
         21 . The method for making a device structure of  claim 20 , wherein said filling step further comprises the steps of: 
 blanket depositing said trench dielectric to a thickness that said trench is overfilled;    polishing said trench dielectric until said capping dielectric and said trench dielectric form one common surface; and    selectively etching down said trench dielectric to said protruded level which is above said top surface.    
     
     
         22 . The method for making a device structure of  claim 19 , wherein in said taking step said substrate is comprising a Si layer on top of said Siege based layer.  
     
     
         23 . The method for making a device structure of  claim 22 , wherein said Si layer is chosen to be between about 1 nm and 50 nm thick.  
     
     
         24 . The method for making a device structure of  claim 23 , wherein said Si layer is tensilely strained.  
     
     
         25 . The method for making a device structure of  claim 19 , wherein in said overlaying step said capping dielectric is chosen to consist essentially of silicon-nitride.  
     
     
         26 . The method for making a device structure of  claim 20 , wherein in said partially consuming step said consuming removes said Si liner in a strip shaped surface on said sidewall, wherein said strip shaped surface runs along a sidewall edge, wherein said trench having said sidewall edge formed where said sidewall intersects said top surface  
     
     
         27 . The method for making a device structure of  claim 20 , wherein in said partially consuming step said grown insulator on said Si liner is chosen to consist essentially of SiO 2 .  
     
     
         28 . The method for making a device structure of  claim 19 , wherein in said partially consuming step said grown insulator on said Si liner is chosen to consist essentially of silicon-oxynitride.  
     
     
         29 . The method for making a device structure of  claim 20 , wherein in said filling step said trench dielectric is chosen to consist essentially of SiO 2 .  
     
     
         30 . The method for making a device structure of  claim 19 , further comprising the step of: 
 depositing an etch protection SiO 2  layer on said substrate prior to said overlaying step.