Method of manufacturing and mounting electronic devices to limit the effects of parasitics

Abstract

A method of producing and mounting electronic devices to negate the effects of parasitics on device performance. In one aspect, the substrate surface of the device is coated with a thin, etch-resistant film during fabrication that acts as a barrier to allow removal of substrate material beneath the film, creating a suspended structure upon which the remaining layers of circuitry rest. Alternatively the device is made with a film that is integral to the device, and that acts as the supporting membrane. To mount the device on a carrier or package, solder bumps are applied near the ends of the conductors of the device, and the die is then secured to a carrier or package, and positioned so that leads extending from the conductors mate up with bonding strips on the carrier or package. The solder bumps are then reflowed or melted to establish electrical connection between leads of the device and corresponding bonding strips of the carrier. The resultant electronic device is essentially immune to the effects or parasitic capacitances and parasitic inductances, with the device as mounted being further configured so as to tune out any residual parasitics which may still exist after fabrication.

What is claimed is:  
     
         1 . An thin film resonator (TFR) device, comprising: 
 a substrate having an etch-resistant thin film thereon; and    a piezoelectric material layer formed between first and second conductors, said first conductor contacting said etch-resistant thin film, the etch-resistant thin film and substrate configured as a suspended membrane supporting said first and second conductors and said piezoelectric layer.    
     
     
         2 . The TFR device of  claim 1 , wherein the etch resistant film acts as a barrier to allow removal of substantially all of said substrate to form a membrane that supports said piezoelectric layer and said first and second conductors.  
     
     
         3 . The TFR device of  claim 1 , wherein said piezoelectric material is a material selected from a group consisting of AlN, SiN and ZnO.  
     
     
         4 . The TFR device of  claim 1 , wherein said first and second conductors are Al metal electrodes or other conductors.  
     
     
         5 . The TFR device of  claim 1 , wherein said substrate is formed of silicon, quartz, or glass.  
     
     
         6 . The TFR device of  claim 1 , wherein said substrate is essentially immune to effects of parasitic capacitance and inductance.  
     
     
         7 . The TFR device of  claim 1 , further comprising a plurality of solder bumps that are applied to ends of leads extending from said first and second conductors, wherein said leads are formed on a die that supports the TFR device.  
     
     
         8 . The TFR device of  claim 7 , 
 wherein the die is attached to a carrier or package intended for the device so that said solder bumps contact corresponding bonding leads on said carrier or package; and    wherein the solder bumps are reflowed to effect electrical connection to the carrier or package.    
     
     
         9 . The TFR device of  claim 8 , wherein the carrier or package connected device is configured so that the effects of any residual parasitic capacitances and parasitic inductances are negated or limited.  
     
     
         10 . An electronic device, comprising: 
 a substrate having an etch-resistant thin film thereon; and    a piezoelectric layer formed between first and second conductor layers, the etch-resistant thin film forming a suspended membrane for supporting the electronic device.    
     
     
         11 . The device of  claim 10 , wherein the etch resistant film thereon acts as a barrier to allow removal of substantially all of said substrate to form the suspended membrane supporting said piezoelectric layer and conductor layers of the electronic device.  
     
     
         12 . The device of  claim 10 , wherein 
 said piezoelectric material is selected from a group consisting of AlN, SiN and ZnO;    said conductive films are Al metal electrodes or other conductors; and    said substrate is formed of silicon, quartz, or glass and is essentially immune to the effects of parasitic capacitance and parasitic inductance.    
     
     
         13 . The device of  claim 10 , further comprising a plurality of solder bumps applied to ends of leads extending from said conductors, wherein said leads are formed on a die that supports the device.  
     
     
         14 . The device of  claim 13 , wherein 
 the die is attached to a package intended for the device so that said solder bumps contact corresponding bonding leads on said package; and    the solder bumps are reflowed to effect electrical connection to the package.