Loop handling for single instruction multiple datapath processor architectures

Abstract

A method of controlling the enabling of processor datapaths in a SIMD processor during a loop processing operation is described. The information used by the method includes an allocation between the data items and a memory, a size of the array, and a number of remaining parallel passes of the datapaths in the loop processing operation. A computer instruction is also provided, which includes a loop handling instruction that specifies the enabling of one of a plurality of processor datapaths during processing an array of data items. The instruction includes a count field that specifies the number of remaining parallel loop passes to process the array and a count field that specifies the number of serial loop passes to process the array. Different instructions can be used to handle different allocations of passes to parallel datapaths. The instruction also uses information about the total number of datapaths.

What is claimed is:  
     
         1 . A method of controlling whether to enable one of a plurality of processor datapaths in a SIMD processor that are operating on data elements in an array, comprising: 
 determining whether to enable the datapath based on information about parameters of the SIMD processor and the array, and a processing state of the datapaths relative to the data items in the array.    
     
     
         2 . The method of  claim 1  wherein the information includes an allocation between the data items and a memory.  
     
     
         3 . The method of  claim 2  wherein the information includes whether the allocation is unity-stride, contiguous, or striped stride.  
     
     
         4 . The method of  claim 1  wherein the information includes a total number of parallel loop passes in a loop processing operation being performed by the datapaths.  
     
     
         5 . The method of  claim 1  wherein the information indicates a size of the array.  
     
     
         6 . The method of  claim 1  wherein the processing state is a number of remaining parallel loop passes in the loop processing operation.  
     
     
         7 . The method of  claim 1  wherein the information includes a number of said processor datapaths.  
     
     
         8 . The method of  claim 1  wherein the information includes an allocation between the data items and a memory, a total number of parallel loop passes in a loop processing operation being performed by the datapaths, a size of the array, a number of remaining parallel passes of the datapaths in the loop processing operation, and a number of said processor datapaths.  
     
     
         9 . The method of  claim 8  wherein the allocation between the data items and the memory is a unity-stride.  
     
     
         10 . The method of  claim 9  wherein the total number of loop passes is determined by dividing a total number of serial loop passes by the total number of datapaths implemented and rounded up to a next integer.  
     
     
         11 . The method of  claim 10  wherein enabling comprises: 
 determining whether the total number of parallel loop passes minus the number of remaining loop passes multiplied by the total number of datapaths implemented plus a datapath number is less than the total number of serial loop passes.  
 
     
     
         12 . The method of  claim 8  wherein the allocation between the data items and the memory is a contiguous stride.  
     
     
         13 . The method of  claim 12  wherein the total number of parallel loop passes is determined by dividing the total number of serial loop passes by the number of datapaths and rounded up to a next integer.  
     
     
         14 . The method of  claim 13  wherein enabling comprises: 
 determining whether the total number of parallel loop passes multiplied by a datapath number plus the total number of parallel loop passes minus a number of remaining parallel loop passes is less than the total number of serial loop passes.  
 
     
     
         15 . The method of  claim 8  wherein the allocation is a striped stride.  
     
     
         16 . The method of  claim 15  wherein enabling comprises: 
 determining whether the total number of parallel loop passes times a datapath number plus the total number of parallel loop passes minus a number of remaining parallel loop passes is less than the total number of serial loop passes.  
 
     
     
         17 . A computer instruction comprising: 
 a loop handling instruction that specifies the enabling of one of a plurality of processor datapaths during processing an array of data items.    
     
     
         18 . The instruction of  claim 17  further comprising: 
 a parallel count field that specifies the number of remaining parallel loop passes to process the array.  
 
     
     
         19 . The instruction of  claim 17  further comprising: 
 a serial count field that specifies the number of serial loop passes to process the array.  
 
     
     
         20 . A processor comprising: 
 a register file;    an arithmetic logic unit coupled to the register file and a program control store that stores a loop handling instruction that causes the processor to enable one of a plurality of processor datapaths during processing of an array of data.