Method and arrangement to determine a clock timing error in a multi-carrier transmission system, and related synchronisation units

Abstract

In a multi-carrier transmission system, a clock timing error (τ e ) is calculated at the receiver's side and used for synchronisation between a transmitting modem and a receiving modem (RX 1 ). The clock timing error (τ e ) is calculated from phase errors (φ 0 , φ 1 , . . . , φ i , . . . , φ N-1 ) detected for a plurality of pilot carriers during a tracking mode in such a way that the share (A i ) of a phase error (φ i ) detected for a particular pilot carrier in the clock timing error (τ e ) depends on the transmission quality (SNR i ) of that pilot carrier over the transmission medium in between the two modems. In this way, the robustness of the synchronisation for norrowband noise near a pilot carrier is improved significantly.

1 . Method to determine during a tracking mode in a multi-carrier system a clock timing error (τ e ) used for synchronisation purposes, said method comprising the steps of detecting phase errors (φ 0 , φ 1 , . . . , φ i , . . . , φ N-1 ) for a plurality of pilot carriers and calculating said clock timing error (τe) from said phase errors (φ 0 , φ 1 , . . . , φ i , φ N-1 ) 
 CHARACTERISED IN THAT a share (A i ) of a phase error (φ i ) of said phase errors (φ 0 , φ 1 , . . . , φ i , . . . , φ N-1 ) in said clock timing error (τ e ) depends on a value (SNR i ) of a transmission quality parameter measured for a pilot carrier of said pilot carriers for whom said phase error (φ i ) is measured.  
 
     
     
         2 . Method according to  claim 1 , 
 CHARACTERISED IN THAT said value (SNR i ) of said transmission quality parameter is determined during an acquisition mode preceding said tracking mode.    
     
     
         3 . Method according to  claim 1 , 
 CHARACTERISED IN THAT said clock timing error (τ e ) is calculated as a weighted sum of said phase errors (φ 0 , φ 1 , . . . , φ i , . . . , φ N-1 ) whereby said share (A i ) of said phase error (φ i ) equals a weight coefficient (A i /B) in said sum.    
     
     
         4 . Method according to  claim 3 , 
 CHARACTERISED IN THAT said share (A i ) is linearly proportional to said value (SNR i ) of said transmission quality parameter.    
     
     
         5 . Method according to  claim 4 , 
 CHARACTERISED IN THAT a proportionality factor between said share (A i ) and said value (SNR i ) of sold transmission quality parameter is linearly dependent on a frequency of said pilot carrier.    
     
     
         6 . Method according to  claim 4 , 
 CHARACTERISED IN THAT said weighted sum is normalised by a linear combination (B) of values (SNR i ) of said transmission quality parameter measured for sold plurality of pilot carriers.    
     
     
         7 . Method according to  claim 6 , 
 CHARACTERISED IN THAT a coefficient in said linear combination (B) depends on a square frequency of a pilot carrier of said pilot carriers.    
     
     
         8 . Method according to  claim 1 , 
 CHARACTERISED IN THAT said transmission quality parameter is a signal-to-noise ratio.    
     
     
         9 . Arrangement (ARR) to determine during a tracking mode in a multi-carrier system a clock timing error (τ e ) used for synchronisation purposes, said arrangement (ARR) comprising: 
 a. phase error detection means (PHASE) whereto a multi-carrier signal is applied, said phase error detection means (PHASE) being adapted to detect phase errors (φ 0 , φ 1 , . . . , φ i , . . . , φ N-1 ) for a plurality of pilot carriers; and  
 b. calculation means (CALC), coupled to said phase error detection means (PHASE), and adopted to calculate said clock timing error (be) from said phase errors (φ 0 , φ 1 , . . . , φ i , . . . , φ N-1 )  
 CHARACTERISED IN THAT said arrangement (ARR) further comprises:  
 c. share determination means (WEIGHT), having an output coupled to said calculation means (CALC) and being adapted to receive via an input thereof values (SNR i ) of a transmission quality parameter related to said plurality of pilot tones and to determine shares (A 0 , A 1 , . . . , A i , . . . , A N-1 ) of said phase errors (φ 0 , φ 1 , . . . , φ i , . . . , φ N-1 ) in said clock timing error (τ e ) from said values (SNR i ) of said transmission quality parameter; and further in that:  
 d. said calculation means (CALC) is adapted to receive via an input thereof said shares (A 0 , A 1 , . . . , A i , . . . , A N-1 ) and to calculate said clock timing error (τ e ) from said shares (A 0 , A 1 , . . . , A i , . . . , A N-1 ) and said phase errors (φ 0 , φ 1 , . . . , φ i , . . . , φ N-1 ).  
 
     
     
         10 . Synchronisation unit (SYNCHRO 1 ) to be used in a multi-carrier system, said synchronisation unit (SYNCHRO 1 ) comprising: 
 a. skip and duplicate means (S/D), adapted to remove a sample from or to duplicate a sample in a multi-carrier signal when a clock timing error (τ e ) becomes larger than or equal to a sample period;    b. phase rotation means (ROTOR), coupled in series with said skip and duplicate means (S/D), and adapted to apply a phase shift to each carrier in said multi-carrier signal proportional to said clock timing error (τ e ) and proportional to a frequency of said carrier;    c. a clock timing error determination arrangement (ARR), coupled to said phase rotation means (ROTOR), and adapted to determine during a tracking mode of said multi-carrier system said clock timing error (τ e ), said clock timing error determination arrangement (ARR) comprising:    c1. phase error detection means (PHASE) whereto a multi-carrier signal is applied, said phase error detection means (PHASE) being adapted to detect phase errors (φ 0 , φ 1 , . . . , φ i , . . . , φ N-1 ) for a plurality of pilot carriers; and    c2. calculation means (CALC), coupled to said phase error detection means (PHASE), and adapted to calculate said clock timing error (τ e ) from said phase errors (φ 0 , φ 1 , . . . , φ i , . . . , φ N-1 ); and    d. a feedback loop (FBL) coupled to said clock timing error determination arrangement (ARR) and having an output coupled to inputs of both said skip and duplicate means (S/D) and said phase rotation means (ROTOR), said feedback loop (FBL) being adapted to feed back said clock timing error (τ e ) to both said skip and duplicate means (S/D) and said phase rotation means (ROTOR),    CHARACTERISED IN THAT said clock timing error determination arrangement (ARR) further comprises:    c3. share determination means (WEIGHT), having an output coupled to said calculation means (CALC) and being adapted to receive via an input thereof values (SNR i ) of a transmission quality parameter related to said plurality of pilot tones and to determine shares (A 0 , A 1 , . . . , A i , . . . , A N-1 ) of said phase errors (φ 0 , φ 1 , . . . , φ i , . . . , φ N-1 ) in said clock timing error (τ e ) from said values (SNR i ) of said transmission quality parameter; and further in that:    c4. said calculation means (CALC) is adapted to receive via an input thereof said shares (A 0 , A 1 , . . . , A i , A . . . , A N-1 ) and to calculate said clock timing error (τ e ) from said shares (A 0 , A 1 , . . . , A i , . . . , A N-1 ) and said phase errors (φ 0 , φ 1 , . . . , φ i , . . . , φ N-1 ).    
     
     
         11 . Synchronisation unit (SYNCHRO 2 ) to be used in a multi-carrier system, said synchronisation unit (SYNCHRO 2 ) comprising: 
 a. sampling means (A/D) under control of a voltage controlled oscillator (VCXO), adopted to sample a multi-carrier signal, a period of said voltage controlled oscillator (VCXO) being controlled by a clock timing error (τ e );    b. phase rotation means (ROTOR), coupled in series with said sampling means (A/D), and adapted to apply a phase shift to each carrier in said multi-carrier signal proportional to a frequency of said carrier;    c. a clock timing error determination arrangement (ARR), coupled to said phase rotation means (ROTOR), and adapted to determine during a tracking mode of said multi-carrier system said clock timing error (τ e ), said clock timing error determination arrangement (ARR) comprising:    c1. phase error detection means (PHASE) whereto a multi-carrier signal is applied, said phase error detection means (PHASE) being adapted to detect phase errors (φ 0 , φ 1 , . . . , φ i , . . . , φ N-1 ) for a plurality of pilot carriers; and    c2. calculation means (CALC), coupled to said phase error detection means (PHASE), and adapted to calculate said clock timing error (τ e ) from said phase errors (φ 0 , φ 1 , . . . , φ i , . . . , φ N-1 ); and    d. a feedback loop (FBL) coupled to said clock timing error determination arrangement (ARR) and having an output coupled to an input of said voltage controlled oscillator (VCXO), said feedback loop (FBL) being adapted to feed back said clock timing error (τ e ) to said voltage controlled oscillator (VCXO),    CHARACTERISED IN THAT said clock timing error determination arrangement (ARR) further comprises:    c3. share determination means (WEIGHT), having an output coupled to said calculation means (CALC) and being adapted to receive via an input thereof values (SNR i ) of a transmission quality parameter related to said plurality of pilot tones and to determine shares (A 0 , A 1 , . . . , A i , . . . , A N-1 ) of said phase errors (φ 0 , φ 1 , . . . , φ i , . . . , φ N-1 ) in said clock timing error (τ e ) from said values (SNR i ) of said transmission quality parameter; and further in that:    c4. said calculation means (CALC) is adapted to receive via an input thereof said shares (A 0 , A 1 , . . . , A i , . . . , A N-1 ) and to calculate said clock timing error (τ e ) from said shares (A 0 , A 1 , . . . , A i , . . . , A N-1 ) and said phase errors (φ 0 , φ 1 , . . . , φ i , . . . , φ N-1 ).    
     
     
         12 . Synchronisation unit (SYNCHRO 3 ) to be used in a multi-carrier system, said synchronisation unit (SYNCHRO 3 ) comprising: 
 a. interpolator means (INT), adapted to receive a multi-carrier input signal and to interpollate in between two successive samples of said multi-carrier input signal to generate an intermediate sample;    b. phase rotation means (ROTOR), coupled in series with said interpolator means (INT), and adapted to apply a phase shift to each carrier in said multi-carrier signal proportional to a frequency of said carrier;    c. a clock timing error determination arrangement (ARR), coupled to said phase rotation means (ROTOR), and adapted to determine during a tracking mode of said multi-carrier system said clock timing error (τ e ), said clock timing error determination arrangement (ARR) comprising:    c1. phase error detection means (PHASE) whereto a multi-carrier signal is applied, said phase error detection means (PHASE) being adapted to detect phase errors (φ 0 , φ 1 , . . . , φ i , . . . , φ N-1 ) for a plurality of pilot carriers; and    c2. calculation means (CALC), coupled to said phase error detection means (PHASE), and adapted to calculate said clock timing error (τ e ) from said phase errors (φ 0 , φ 1 , . . . , φ i , . . . , φ N-1 ); and    d. a feedback loop (FBL) coupled to said clock timing error determination arrangement (ARR) and having an output coupled to an input of both said skip and duplicate means (S/D) and said interpolator means (INT), said feedback loop (FBL) being adapted to feed back said clock timing error (τ e ) to both said skip and duplicate means (S/D) and said interpolator (INT);    CHARACTERISED IN THAT said clock timing error determination arrangement (ARR) further comprises:    c3. share determination means (WEIGHT), having an output coupled to said calculation means (CALC) and being adapted to receive via an input thereof values (SNR i ) of a transmission quality parameter related to said plurality of pilot tones and to determine shares (A 0 , A 1 , . . . , A i , . . . , A N-1 ) of said phase errors (φ 0 , φ 1 , . . . , φ i , . . . , φ N-1 ) in said clock timing error (τ e ) from said values (SNR i ) of said transmission quality parameter; and further in that:    c4. said calculation means (CALC) is adapted to receive via an input thereof said shares (A 0 , A 1 , . . . , A i , . . . , A N-1 ) and to calculate said clock timing error (τ e ) from said shares (A 0 , A 1 , . . . , A i , . . . , A N-1 ) and said phase errors (φ 0 , φ 1 , . . . , φ i , . . . , φ N-1 ).