[chip package structure and manufacturing process thereof]

Abstract

A chip package structure and manufacturing process thereof is provided. The manufacturing method uses fine pitch circuit processes, such as a TFT-LCD process or an IC process, to increase layout density and shorten electrical transmission pathways so that a higher electrical performance level is attained. First, a multi-layered interconnection structure with high-density bonding pads and fine pitch circuit is formed over a hard support base plate having a large area and high degree of planarity. A die is attached to a top surface of the multi-layered interconnection structure. A plurality of opening is formed on a bottom surface of the support base plate. Contacts are positioned into the openings in the support base plate such that the contacts are electrically connected to an inner circuit within the multi-layered interconnection structure.

1 . A chip package structure, at least comprising: 
 a multi-layered interconnection structure having a top surface and a back surface, wherein the multi-layered interconnection structure furthermore comprises an inner circuit and that the inner circuit furthermore comprises a plurality of bonding pads located on the bottom surface of the multi-layered interconnection structure;    at least a die set up on the top surface of the multi-layered interconnection structure, wherein the die is electrically connected to the inner circuit within the multi-layer interconnection structure; and    a support base plate fabricated using an insulating material, wherein the support base plate is set up on the bottom surface of the multi-layered interconnection structure, and that the support base plate furthermore comprises a plurality of first openings that exposes the respective bonding pads.    
     
     
         2 . The chip package structure of  claim 1 , wherein the package furthermore comprises an isolating base layer fabricated using an insulating material and positioned between the multi-layered interconnection structure and the support base plate, and that the isolating base layer has a plurality of second openings that exposes the respective bonding pads.  
     
     
         3 . The chip package structure of  claim 1 , wherein the support base plate is fabricated using a material selected from a group consisting of glass, quartz and ceramics.  
     
     
         4 . The chip package structure of  claim 1 , wherein the package furthermore comprises a plurality of contacts with each contact connected to a bonding pad through a corresponding first opening.  
     
     
         5 . The chip package structure of  claim 4 , wherein the contact has a profile selected from a group consisting of solder ball, pin and electrode block.  
     
     
         6 . The chip package structure of  claim 1 , wherein the die is electrically connected to the inner circuit within the multi-layered interconnection structure by performing a flip chip process.  
     
     
         7 . The chip package structure of  claim 1 , wherein the die is electrically connected to the inner circuit within the multi-layered interconnection structure by performing a wire-bonding process.  
     
     
         8 . The chip package structure of  claim 1 , wherein the die is electrically connected to the inner circuit within the multi-layered interconnection structure by performing a thermal compression bonding process.  
     
     
         9 . The chip package structure of  claim 1 , wherein the inner circuit has a line width between about 1 Âμm to 50 Âμm.  
     
     
         10 . The chip package structure of  claim 1 , wherein the inner circuit has a line pitch between about 1 Âμm to 50 Âμm.  
     
     
         11 . The chip package structure of  claim 1 , wherein the package furthermore comprises at least a passive component set up within the multi-layered interconnection structure and connected to the inner circuit within the multi-layered interconnection structure.  
     
     
         12 . The chip package structure of  claim 1 , wherein the package furthermore comprises at least a passive component set up on the top surface of the multi-layered interconnection structure and electrically connected to the inner circuit within the multi-layered interconnection structure.  
     
     
         13 . A method of fabricating a chip package, at least comprising the steps of: 
 providing a support base plate having a top surface and a back surface;    forming a multi-layered interconnection structure over the top surface of the support base plate, wherein the multi-layered interconnection structure has an inner circuit with a plurality of bonding pads on a surface of the multi-layered interconnection structure closest to the support base plate;    attaching at least a die on a surface of the multi-layered interconnection structure furthest from the support base plate, wherein the die is electrically connected to the inner circuit within the multi-layered interconnection structure; and    forming a plurality of first openings on the support base plate, wherein each first opening exposes a corresponding bonding pad.    
     
     
         14 . The method of  claim 13 , wherein the support base plate is fabricated using a material selected from a group consisting of glass, quartz and ceramics.  
     
     
         15 . The method of  claim 13 , wherein after the step of forming a plurality of first openings, further includes forming a plurality of contacts on the bottom surface of the support base plate, and each contact electrically connects with a corresponding bonding pad through the first opening.  
     
     
         16 . The method of  claim 15 , wherein the contact has a profile selected from a group consisting of solder ball, pin and electrode block.  
     
     
         17 . The method of  claim 13 , wherein the inner circuit has a line width between about 1 Âμm to 50 Âμm.  
     
     
         18 . The method of  claim 13 , wherein the inner circuit has a line pitch between about 1 Âμm to 50 Âμm.  
     
     
         19 . The method of  claim 13 , wherein the step of forming a multi-layered interconnection structure over the support base plate furthermore includes forming at least a passive component on a surface of the multi-layered interconnection structure furthest away from the support base plate such that the passive component is electrically connected to the inner circuit within the multi-layered interconnection structure.  
     
     
         20 . The method of  claim 13 , wherein the step of forming a multi-layered interconnection structure over the support base plate furthermore includes forming at least a passive component inside the multi-layered interconnection structure such that the passive component is electrically connected to the inner circuit within the multi-layered interconnection structure.  
     
     
         21 . The method of  claim 13 , wherein after the step of providing a support base plate, furthermore includes forming an isolating base layer over the top surface of the support base plate, and instead of the step of forming a multi-layered interconnection structure over the support base plate, forming the multi-layered interconnection structure over the isolating base layer, and after the step of forming a plurality of first openings on the support base plate, furthermore includes forming a plurality of second openings in the isolating base layer such that each second openings links with one of the first openings to expose a corresponding bonding pad.  
     
     
         22 . The method of  claim 13 , wherein the step of attaching a die onto a surface of the multi-layered interconnection structure includes performing a flip chip bonding process, a wire-bonding process or a thermal compression bonding process.  
     
     
         23 . The method of  claim 13 , wherein after the step of forming a multi-layered interconnection structure over the top surface of the support base plate but before the step of attaching a die to a surface of the multi-layered interconnection structure, furthermore includes reducing the thickness of the support base plate.  
     
     
         24 . The method of  claim 13 , wherein after attaching a die to a surface of the multi-layered interconnection structure but before forming a plurality of first openings on the support base plate, furthermore includes reducing the thickness of the support base plate.  
     
     
         25 . The method of  claim 13 , wherein after forming a plurality of first openings on the support base plate, furthermore includes reducing the thickness of the support base plate.  
     
     
         26 . The method of  claim 13 , wherein the step of forming a plurality of first openings on the support base plate includes ultrasonic piercing, laser drilling or photolithographic processing and etching.