TTO nitride liner for improved collar protection and TTO reliability

Abstract

A structure and method which enables the deposit of a thin nitride liner just before Trench Top Oxide TTO (High Density Plasma) HDP deposition during the formation of a vertical MOSFET DRAM cell device. This liner is subsequently removed after TTO sidewall etch. One function of this liner is to protect the collar oxide from being etched during the TTO oxide sidewall etch and generally provides lateral etch protection which is not realized in the current processing scheme. The process sequence does not rely on previously deposited films for collar protection, and decouples TTO sidewall etch protection from previous processing steps to provide additional process flexibility, such as allowing a thinner strap Cut Mask nitride and greater nitride etching during node nitride removal and buried strap nitrided interface removal. Advantageously, the presence of the nitride liner beneath the TTO reduces possibility of TTO dielectric breakdown between the gate and capacitor node electrode of the vertical MOSFET DRAM cell, while assuring strap diffusion to gate conductor overlap.

1 . A DRAM cell array which comprises: 
 a plurality of memory cells which are arranged in rows and columns, each memory cell including a deep trench having a vertical MOSFET and an underlying capacitor formed therein that are in electrical contact to each other through at least one buried-strap out diffusion region which is present within a portion of a wall of each deep trench;    each memory cell having a deep trench conductor forming an electrode of said underlying capacitor and a collar oxide region formed in a portion of the deep trench;    the collar oxide region formed on a remaining wall portion of each deep trench not containing said buried-strap out diffusion region for electrically isolating a body region from said underlying capacitor;    a trench top oxide (TTO) layer formed on a horizontal surface of the DRAM cell array for isolating the deep trench conductor forming an electrode of said underlying capacitor and said buried-strap out diffusion region from a gate conductor region;    an underlying nitride layer formed immediately adjacent to and contacting a top of a sacrificial oxide layer formed immediately adjacent to and contacting a top of said deep trench conductor between the top of immediately adjacent to and contacting a top of said deep trench conductor and said buried-strap out diffusion region and underlying said TTO layer to eliminate a possibility of TTO layer dielectric breakdown between said gate conductor region and said electrode of said underlying capacitor.    
     
     
         2 . The DRAM cell array of  claim 1 , wherein said nitride layer is deposited to a thickness ranging from 1.0 nm-10.0 nm.  
     
     
         3 . The DRAM cell array of  claim 1 , wherein each said vertical MOSFET includes gate dielectrics formed on inner surfaces of said sidewalls of each said deep trench.  
     
     
         4 . The DRAM cell array of  claim 1 , wherein the underlying nitride layer is formed only under and on the side of the TTO layer.