Method of forming vertical mosfet with ultra-low on-resistance and low gate charge

Abstract

A vertical trench double-diffused metal-oxide-semiconductor (DMOS) field effect transistor characterized by a reduced drain-to-source resistance and a lower gate charge and providing a high transconductance and an enhanced frequency response.

What is claimed is:  
     
         1 . A method of forming a field effect transistor, comprising: 
 providing a silicon substrate of a first conductivity type;    forming a substrate cap layer of the first conductivity type over the silicon substrate;    epitaxially forming a body layer of a second conductivity type over the substrate cap layer;    forming a trench extending through the body layer and the substrate cap layer, the trench having a bottom and sidewalls; and    forming a source region of the first conductivity type in the body layer adjacent the trench,    wherein a substrate out-diffusion region of the first conductivity type is formed between the substrate cap layer and the source regions such that a spacing between each source region and the substrate out-diffusion region defines a channel length of the field effect transistor.    
     
     
         2 . The method of  claim 1  further comprising: 
 lining the sidewalls and bottom of the trench with a dielectric material; and  
 lining the dielectric material with a conductive material and substantially filling the trench with the conductive material.  
 
     
     
         3 . The method of  claim 2  wherein a thickness of the dielectric material at the bottom of the trench is thicker than a thickness of the dielectric material on the sidewalls of the trench.  
     
     
         4 . The method of  claim 2  further comprising: 
 forming a dielectric plug at the bottom of each trench using high density plasma chemical vapor deposition.  
 
     
     
         5 . The method of  claim 2  further comprising: 
 forming a dielectric plug at the bottom of each trench using sub-atmospheric chemical vapor deposition.  
 
     
     
         6 . The method of  claim 2  wherein: 
 the trench extends through the substrate out-diffusion region, and  
 the conductive material in the trench extends through a substantial depth of the substrate out-diffusion region.  
 
     
     
         7 . The method of  claim 1  wherein the trench extends partially into the silicon substrate.  
     
     
         8 . The method of  claim 1  wherein the substrate out-diffusion region has a graded doping concentration decreasing from a surface of the substrate out-diffusion region at an interface between the substrate out-diffusion region and the substrate cap layer to an opposing surface of the substrate out-diffusion region.  
     
     
         9 . The method of  claim 1  wherein the substrate cap layer has a lower doping concentration than that of the silicon substrate.  
     
     
         10 . The method of  claim 1  wherein the channel length extends vertically along a sidewall of the trench.  
     
     
         11 . The method of  claim 1  further comprising: 
 administering a channel implant to change a threshold voltage of the field effect transistor.  
 
     
     
         12 . A method of forming a field effect transistor, comprising: 
 providing a silicon substrate of a first conductivity type;    forming a substrate cap layer of the first conductivity type over the silicon substrate;    epitaxially forming a body layer of a second conductivity type over the substrate cap layer;    forming a plurality of trenches each extending through the body layer and the substrate cap layer, each trench having a bottom and sidewalls;    lining the sidewalls and bottom of each trench with a dielectric material;    lining the dielectric material with a conductive material and substantially filling each trench with the conductive material; and    forming a plurality of source regions of the first conductivity type in the body layer adjacent the plurality of trenches,    wherein a substrate out-diffusion region of the first conductivity type is formed such that a spacing between each source region and the substrate out-diffusion region defines a channel length of the field effect transistor, the channel length extending vertically along a sidewall of each trench.    
     
     
         13 . The method of  claim 12  wherein: 
 the plurality of trenches extend through the substrate out-diffusion region, and  
 the conductive material in each trench extends through a substantial depth of the substrate out-diffusion region.  
 
     
     
         14 . The method of  claim 12  wherein the dielectric material in each trench is thicker along the bottom of each trench than along the sidewalls of each trench.  
     
     
         15 . The method of  claim 12  further comprising: 
 forming a dielectric plug along the bottom of each trench so that each trench has a thicker dielectric material along its bottom than along its sidewalls.  
 
     
     
         16 . The method of  claim 15  wherein the dielectric plug in each trench is formed using high density plasma chemical vapor deposition.  
     
     
         17 . The method of  claim 16  wherein the dielectric plug in each trench is formed using sub-atmospheric chemical vapor deposition.  
     
     
         18 . The method of  claim 12  wherein the substrate out-diffusion region has a graded doping concentration decreasing from a surface of the substrate out-diffusion region at an interface between the substrate out-diffusion region and the substrate cap layer to an opposing surface of the substrate out-diffusion region.  
     
     
         19 . The method of  claim 18  wherein the substrate cap layer has a lower doping concentration than that of the silicon substrate.  
     
     
         20 . The method of  claim 12  wherein each trench extends partially into the silicon substrate.  
     
     
         21 . The method of  claim 12  wherein the substrate out-diffusion region has a thickness of less than or equal to one micrometer.  
     
     
         22 . The method of  claim 12  further comprising: 
 administering a channel implant to change a threshold voltage of the field. effect transistor.