Method and apparatus for coding bits of data in parallel

Abstract

A concatenated encoder capable of coding multiple data bits in parallel and including a first (outer) encoder, a memory, and a second (inner) encoder coupled in cascade. The first encoder receives and codes M data bits in parallel in accordance with a first coding scheme to generate MR code bits. The memory receives and stores unpunctured ones of the MR code bits from the first encoder. The second encoder receives and codes N code bits in parallel in accordance with a second coding scheme to generate coded data. M and N can be any values (e.g., M≧8, N≧4). Each encoder can be a (e.g., a rate ½) convolutional encoder that implements a particular polynomial generator, and can be implemented with one or more look-up tables, a state machine, or some other design.

What is claimed is:  
     
         1 . An apparatus, comprising: 
 a clock means for generating a clock signal having a clock cycle;    a plurality of serially coupled registers, wherein each register is updated on one clock cycle; and    means for generating a future state of the plurality of registers in response to an input to the plurality of serially coupled registers.    
     
     
         2 . An apparatus, comprising: 
 an encoder, comprising: 
 a plurality of delay elements, wherein a state of the encoder is determined by the state of the plurality of delay elements; and  
 a look up table for mapping of a current state of the encoder to a future state of the encoder.