Insulated gate field effect transistor and method of fabricating the same

Abstract

A first object of the present invention is to provide an insulated gate field effect transistor which realizes reductions in the junction depth and the resistance of source and drain junction regions beneath a gate electrode. Another object is to provide a miniaturized complementary type insulated gate field effect transistor capable of achieving a large current and a high operation speed. In a miniaturized MOS transistor, a low concentration impurity integrated layer comprising In or Ga is provided so as to have a peak in the inside of high concentration shallow source and drain diffusion layer regions. By this arrangement, the shallow source and drain diffusion layers are attracted by the impurity integrated layer, to realize shallower junctions having a high concentration and a rectangular distribution. As a result, particularly, a miniaturized PMOS with a larger current punch-through hard and an ultra miniaturized configuration is achieved, and this can be applied also to NMOS, and, therefore, a CMOS with a larger current, punch-through hard and a more miniaturized configuration can be achieved without complicating the fabrication steps, namely, economically.

What is claimed is:  
     
         1 . An insulated gate field effect transistor comprising a PN junction at a portion of a main surface region of a semiconductor substrate of a first conductive type, said PN junction formed by a high concentration impurity region of a second conductive type demarcated by a deep junction and a shallow junction, said high concentration impurity region so constituted as to have a maximum concentration at the surface of said semiconductor substrate, and a second impurity region distributed in the inside of said high concentration region of a first impurity constituting said shallow junction region of said second conductive type, said second impurity region having a maximum concentration in the inside of said semiconductor and having a maximum concentration lower than the maximum impurity concentration of said high concentration region of said first impurity.  
     
     
         2 . An insulated gate field effect transistor as set forth in  claim 1 , wherein the maximum concentration of said first impurity region constituting said shallow junction region is not less than 1×10 20  cm −3 , and the maximum impurity concentration of said second impurity region is not more than 5×10 19  cm −3 .  
     
     
         3 . An insulated gate field effect transistor as set forth in  claim 1 , wherein the impurity constituting said second impurity region is In.  
     
     
         4 . An insulated gate field effect transistor as set forth in  claim 3 , wherein said first and second high concentration impurity regions constituting said shallow junction regions are constituted of As and B.  
     
     
         5 . An insulated gate field effect transistor as set forth in  claim 3 , wherein said high concentration impurity region constituting said deep junction and said shallow junction is a source region and a drain region.  
     
     
         6 . An insulated gate field effect transistor as set forth in  claim 3 , wherein said high concentration impurity region constituting said deep junction and said shallow junction is a source region.  
     
     
         7 . An insulated gate field effect transistor as set forth in  claim 5 , wherein an impurity region of a conductive type opposite to that of said source region is provided so as to surround said source region having said shallow junction and to have a maximum impurity concentration at said shallow source junction depth.  
     
     
         8 . An insulated gate field effect transistor as set forth in  claim 6 , wherein an impurity region of a conductive type opposite to that of said source region is provided so as to surround said source region having said shallow junction and to have a maximum impurity concentration at said shallow source junction depth.  
     
     
         9 . An insulated gate field effect transistor wherein a first conduction type region and a second conduction type region are provided at main surface portions of the same semiconductor substrate, a first insulated gate field effect transistor comprising a PN junction formed by a high concentration impurity region of a second conduction type demarcated by a deep junction and a shallow junction is provided in said first conduction type region, whereas a second insulated gate field effect transistor comprising a PN junction formed by a high concentration impurity region of a first conduction type demarcated by a deep junction and a shallow junction is provided in said second conduction type region, and a second impurity region having a maximum concentration in the inside of said semiconductor substrate is provided in said high concentration impurity region of said second conduction type constituting said shallow junction and in said high concentration impurity region of said first conduction type.  
     
     
         10 . An insulated gate field effect transistor as set forth in  claim 9 , wherein the maximum impurity concentration of said first and second conduction type high concentration impurity regions constituting said shallow junction regions is not less than 1×10 20  cm −3 , and the maximum impurity concentration of said second impurity region is not more than 5×10 19  cm −3 .  
     
     
         11 . An insulated gate field effect transistor as set forth in  claim 9 , wherein the impurity constituting said second impurity region is In.  
     
     
         12 . An insulated gate field effect transistor as set forth in  claim 11 , wherein said first and second high concentration impurity regions constituting said shallow junction regions are constituted of As and B.  
     
     
         13 . An insulated gate field effect transistor as set forth in  claim 11 , wherein said high concentration impurity region constituting said deep junction and said shallow junction is a source region and a drain region.  
     
     
         14 . An insulated gate field effect transistor as set forth in  claim 11 , wherein said high concentration impurity region constituting said deep junction and said shallow junction is a source region.  
     
     
         15 . An insulated gate field effect transistor as set forth in  claim 13 , wherein an impurity region of a conduction type opposite to that of said source region is provided so as to surround said source region having said shallow junction and to have a maximum impurity concentration at said shallow source junction depth.  
     
     
         16 . An insulated gate field effect transistor as set forth in  claim 14 , wherein an impurity region of a conduction type opposite to that of said source region is provided so as to surround said source region having said shallow junction and to have a maximum impurity concentration at said shallow source junction depth.  
     
     
         17 . A method of fabricating an insulated gate field effect transistor comprising the steps of: forming a gate electrode; introducing a first impurity of a second conductive type so as to obtain a maximum impurity concentration at a main surface of a semiconductor substrate by using an end of said gate electrode as an introduction boundary; and introducing a second impurity region of the second conductive type so as to obtain a maximum impurity concentration in said first impurity introduction region in said semiconductor substrate.  
     
     
         18 . A method of fabricating an insulated gate field effect transistor as set forth in  claim 17 , comprising a step of introducing said first impurity so as to obtain a maximum impurity concentration at a main surface of said semiconductor substrate after the step of introducing said second impurity region.  
     
     
         19 . A method of fabricating an insulated gate field effect transistor as set forth in  claim 17 , comprising a step of introducing an impurity region of a conductive type opposite to that of said first impurity so as to surround at least a bottom surface region of said first impurity introduction region of said second conductive type by using an end of said gate electrode as an introduction boundary.  
     
     
         20 . A method of fabricating an insulated gate field effect transistor as set forth in  claim 19 , comprising the steps of: forming an insulation film at a side wall of said gate electrode; and introducing an impurity region of a conductive type opposite to that of said first impurity by using an end of said gate electrode side wall insulation film as an introduction boundary.  
     
     
         21 . A method of fabricating an insulated gate field effect transistor as set forth in  claim 17 , comprising a step of activation heat treatment in the process of a step of sequentially introducing impurities of a first conductive type or a second conductive type by using said gate electrode or said gate side wall insulation film as an introduction boundary.  
     
     
         22 . A method of fabricating an insulated gate field effect transistor, comprising the steps of: forming a gate electrode above a main surface of each of a first conductive type region and a second conductive type region formed in main surface regions of a semiconductor substrate, with a gate insulation film therebetween; selectively introducing a second conductive type high concentration impurity into said first conductive type region and a first conductive type high concentration impurity into said second conductive type region by using each of ends of said gate electrodes as an introduction boundary; and introducing a second conductive type impurity different from said second conductive type high concentration impurity.  
     
     
         23 . A method of fabricating an insulated gate field effect transistor as set forth in  claim 22 , comprising a step of introducing a first conductive type impurity region so as to surround at least a bottom surface region of said second conductive type high concentration impurity region and introducing a second conductive type impurity region so as to surround at least a bottom surface region of said first conductive type high concentration impurity region, by using each of ends of said gate electrodes as an introduction boundary.  
     
     
         24 . A method of fabricating an insulated gate field effect transistor as set forth in  claim 23 , wherein at least one of said first and second conductive type impurity regions introduced so as to surround at least the bottom surface regions of said high concentration impurity regions respectively is introduced by using an end of a gate electrode side wall insulation film as an introduction boundary.  
     
     
         25 . A method of fabricating an insulated gate field effect transistor as set forth in  claim 22 , comprising a step of introducing a second conductive type impurity different from said second conductive type high concentration impurity, after introducing said first conductive type high concentration impurity or said second conductive type high concentration impurity and conducting an activation heat treatment.  
     
     
         26 . A method of fabricating an insulated gate field effect transistor as set forth in  claim 22 , comprising a step of introducing a second conductive type impurity different from said second conductive type high concentration impurity, before introducing said first conductive type high concentration impurity or said second conductive type high concentration impurity.