US2004124546A1PendingUtilityA1

Reliable integrated circuit and package

Priority: Dec 29, 2002Filed: Sep 9, 2003Published: Jul 1, 2004
Est. expiryDec 29, 2022(expired)· nominal 20-yr term from priority
H10W 90/754H10W 74/00H10W 72/5449H10W 72/5363H10W 72/01515H10W 72/983H10W 72/952H10W 72/951H10W 72/932H10W 72/923H10W 72/536H10W 72/534H10W 72/075H10W 72/59H10W 72/29H10W 74/127H10W 72/90H10W 42/00
40
PatentIndex Score
0
Cited by
0
References
0
Claims

Abstract

A packaged integrated circuit which includes a die 700 having a surface and corners separated by edges. The die surface includes depressions 600, 720 so that mold compound 114 covering the die surface fills the depressions. The filling of the depressions in the die surface enhances the adhesion of the mold compound to the die. The die can include bond pads 714 , in which case the depressions can take the form of slots 720 in the bond pads. In addition, the depressions can take the form of trenches 600 at the surface of the die in a dielectric layer 703 . The trenches can be at the die corners and along the die edges.

Claims

exact text as granted — not AI-modified
We claim:  
     
         1 . A packaged integrated circuit, comprising: 
 a die having a surface and corners separated by edges, said die surface including depressions; and    mold compound covering said die surface and filling said depressions.    
     
     
         2 . The packaged integrated circuit of  claim 1 , wherein said die comprises bond pads, and further wherein said depressions comprise slots in said bond pads.  
     
     
         3 . The packaged integrated circuit of  claim 1 , wherein said depressions comprise trenches at the surface of said die in a dielectric layer.  
     
     
         4 . The packaged integrated circuit of  claim 3 , wherein said trenches are at said corners of said die.  
     
     
         5 . The packaged integrated circuit of  claim 4 , wherein said trenches are along said edges of said die.  
     
     
         6 . The packaged integrated circuit of  claim 1 , wherein said surface of said die comprises step-like projections, and further wherein said die surface and said projections are covered with a passivating dielectric, wherein said dielectric covering said step-like projections has sloped edges.  
     
     
         7 . A packaged integrated circuit, comprising: 
 a die comprising a stack of alternating patterned metal and dielectric layers;    a trench in said stack through at least one of said dielectric layers; and    mold compound covering said die and filling said trench.    
     
     
         8 . The packaged integrated circuit of  claim 7 , wherein said stack includes a highest layer of patterned metal and a next-highest layer of patterned metal separated by an inter-level dielectric layer, and further wherein said trench is formed in said interlevel dielectric layer.  
     
     
         9 . The packaged integrated circuit of  claim 8 , further comprising a dummy pad formed in said next-highest layer of patterned metal, wherein said trench is formed in said interlevel dielectric layer over said dummy pad.  
     
     
         10 . The packaged integrated circuit of  claim 7 , wherein said trench is formed at a corner of said die.  
     
     
         11 . The packaged integrated circuit of  claim 7 , wherein said trench is formed along the edges of said die.  
     
     
         12 . The packaged integrated circuit of  claim 7 , wherein said die includes bond pads, said bond pads including slots.  
     
     
         13 . The packaged integrated circuit of  claim 7 , wherein said die comprises step-like projections, and further wherein said die and said projections are covered with a passivating dielectric, wherein said dielectric covering said step-like projections has sloped edges.  
     
     
         14 . A packaged integrated circuit, comprising: 
 a die including bond pads, wherein each of said bond pads comprise a central bonding region and a peripheral region, said peripheral region comprising at least one slot.    
     
     
         15 . The packaged integrated circuit of  claim 14 , further comprising a passivating dielectric layer over said die, said passivating dielectric layer conformally covering said bond pad and said slots.  
     
     
         16 . The packaged integrated circuit of  claim 14 , further comprising mold compound covering said die and filling said slots.  
     
     
         17 . The packaged integrated circuit of  claim 15  further comprising mold compound covering said die and filling said slots.  
     
     
         18 . The packaged integrated circuit of  claim 17  further comprising a trench in a surface of said die, wherein said mold compound fills said trench.  
     
     
         19 . The packaged integrated circuit of  claim 18 , wherein said trench is at a corner of said die.  
     
     
         20 . The packaged integrated circuit of  claim 14 , wherein said bond pads are covered with a passivating dielectric having sloped edges.

Join the waitlist — get patent alerts

Track US2004124546A1 — get alerts on status changes and closely related new filings.

We store only your email — no account needed. See our privacy policy.