Etch stop layer

Abstract

A SiOC layer and/or a SiC layer of an etch stop layer may be improved by altering the process used to form them. In a bi-layer structure, a SiOC layer and/or a SiC layer may be improved to provide better reliability. A silicon carbide (SiC) layer may be used to form a single-layer etch stop layer, while also acting as a glue layer to improve interface adhesion. Preferably, the SiC layer is formed in a reaction chamber having a flow of substantially pure trimetholsilane (3MS) streamed into and through the reaction chamber under a pressure of less than about 2 torr therein. Preferably, the reaction chamber is energized with high frequency RF power of about 100 watts or more. Preferably, the SiOC layer is formed in a reaction chamber having a flow of 3MS and CO 2 , and is energized with low frequency RF power of about 100 watts or more.

What is claimed is:  
     
         1 . A method of manufacturing a semiconductor device, comprising: 
 forming a layer of silicon carbide (SiC) directly on an underlying layer;    forming a dielectric layer directly on the SiC layer, the dielectric layer having a top surface;    etching the dielectric layer to form an opening therein with a first etch chemistry, wherein the SiC layer acts as an etch stop layer;    depositing a conducting material into the opening and on the top surface of the dielectric; and    removing a portion of the conducting material so that a top surface of the conducting material is substantially planar with the top surface of the dielectric layer.    
     
     
         2 . The method of  claim 1 , etching the SiC layer at the opening with a second etch chemistry.  
     
     
         3 . The method of  claim 1 , wherein the etching of the dielectric layer includes a dual damascene process for forming the opening.  
     
     
         4 . The method of  claim 1 , wherein the first etch chemistry is selective against etching SiC.  
     
     
         5 . The method of  claim 1 , wherein SiC layer has a thickness between about 20 angstroms and about 550 angstroms, wherein the underlying layer is an oxide layer formed over a plurality of CMOS transistors, and wherein the dielectric layer is composed of a dielectric material including a diamond-structured carbon material.  
     
     
         6 . The method of  claim 1 , wherein the removing of the conducting material portion is by polishing.  
     
     
         7 . The method of  claim 1 , wherein the forming of the SiC layer further comprises: 
 flowing substantially pure trimetholsilane (3MS) into a reaction chamber having a pressure of less than about 2 torr therein.    
     
     
         8 . The method of  claim 7 , wherein the flowing of the 3MS occurs at a flow rate of about 150 sccm, wherein the reaction chamber has a temperature of about 350° C. therein, and wherein high frequency RF power of at least about 100 watts is applied in the reaction chamber to induce the formation of the SiC layer on the underlying layer.  
     
     
         9 . The method of  claim 8 , wherein the pressure within the reaction chamber is about 1.7 torr.  
     
     
         10 . A semiconductor device comprising: 
 a first silicon carbide (SiC) layer formed directly on an underlying layer;    a first dielectric layer formed directly on the SiC layer, the first dielectric layer having a top surface; and    a first conductor extending through the first dielectric layer and the first SiC layer, the first conductor having a top surface, and wherein the top surface of the first conductor is substantially planar with the top surface of the dielectric layer.    
     
     
         11 . The device of  claim 10 , wherein the SiC layer has a thickness of about 550 angstroms.  
     
     
         12 . The device of  claim 10 , wherein the SiC layer acts as a glue layer and as an etch stop layer.  
     
     
         13 . The device of  claim 10 , wherein the first conductor is composed of a conducting material that includes copper.  
     
     
         14 . The device of  claim 10 , wherein the first dielectric layer is composed of a dielectric material including a diamond-structured carbon material.  
     
     
         15 . The device of  claim 10 , wherein the first dielectric layer is composed of a dielectric material including a SiOCH material.  
     
     
         16 . The device of  claim 10 , wherein the first dielectric layer is composed of SiOC.  
     
     
         17 . The device of  claim 10 , wherein the underlying layer is an oxide layer.  
     
     
         18 . The device of  claim 17 , further comprising a plurality of CMOS transistors being covered by the oxide layer.  
     
     
         19 . The device of  claim 10 , further comprising: 
 a second silicon carbide (SiC) layer formed directly on the first dielectric layer;    a second dielectric layer formed directly on the second SiC layer;    a second conductor extending through the second dielectric layer and the second SiC layer and connecting to the first conductor.    
     
     
         20 . The device of  claim 19 , further comprising: 
 a third silicon carbide (SiC) layer formed directly on the second dielectric layer;    a third dielectric layer formed directly on the third SiC layer;    a third conductor extending through the third dielectric layer and the third SiC layer and connecting to the second conductor;    a fourth silicon carbide (SiC) layer formed directly on the third dielectric layer;    a fourth dielectric layer formed directly on the fourth SiC layer; and    a fourth conductor extending through the fourth dielectric layer and the fourth SiC layer and connecting to the third conductor.    
     
     
         21 . The device of  claim 20 , wherein each of the first, second, third, and fourth conductors are composed of a conducting material that includes copper, and wherein each of the first, second, third, and fourth dielectric layers is composed of a low-k dielectric material selected from a group consisting of SiCOH and diamond-structured carbon.  
     
     
         22 . A semiconductor device comprising: 
 a plurality of transistors, each of the transistors having a channel length of 130 nm or less;    an oxide layer overlying the plurality of transistors;    a silicon carbide (SiC) layer formed directly on the oxide layer;    a dielectric layer formed directly on the SiC layer, the dielectric layer having a top surface;    a conducting material disposed within a trench formed in the dielectric layer, the conducting material having a top surface, wherein the top surface of the conducting material is substantially planar with the top surface of the dielectric layer; and    a contact extending through the dielectric layer and the SiC layer to connect one of the transistors to the conducting material.    
     
     
         23 . The device of  claim 22 , wherein the transistors are CMOS transistors.  
     
     
         24 . The device of  claim 22 , wherein the SiC layer has a thickness between about 20 angstroms and about 600 angstroms.  
     
     
         25 . A method of manufacturing a semiconductor device, comprising: 
 forming a silicon carbide (SiC) etch stop layer on an underlying layer in a reaction chamber with a process comprising: 
 flowing substantially pure trimetholsilane (3MS) into and through the reaction chamber, and  
 pressurizing the reaction chamber at a pressure less than about 2 torr; and  
   forming a dielectric layer over the SiC layer.    
     
     
         26 . The method of  claim 25 , wherein a flow rate of the 3MS flowing is about 150 sccm, and wherein the process of forming the SiC layer further comprises: 
 energizing the reaction chamber with high frequency RF power of at least about 100 watts; and    heating the reaction chamber to a temperature of about 350° C.    
     
     
         27 . A semiconductor device comprising: 
 a layer of silicon carbide (SiC) material formed on an underlying layer, wherein the SiC material has a current leakage of less than about 1.0×10 −6  amps per square centimeter at an electric field of about 2 megavolts per centimeter;    a dielectric layer formed over the SiC layer; and    a conductor extending through the dielectric layer and the SiC layer.    
     
     
         28 . The semiconductor device of  claim 27 , wherein the current leakage at about 2 megavolts per centimeter is about 1.5×10 −8  amps per square centimeter.  
     
     
         29 . The semiconductor device of  claim 27 , wherein the current leakage at about 1 megavolts per centimeter is about 1.0×10 −9  amps per square centimeter.  
     
     
         30 . A method of manufacturing a semiconductor device, comprising: 
 forming a SiOC etch stop layer over an underlying layer in a reaction chamber with a process comprising: 
 flowing trimetholsilane (3MS) into and through the reaction chamber,  
 flowing CO 2  into and through the reaction chamber,  
 pressurizing the reaction chamber at a pressure less than about 2 torr, and  
 energizing the reaction chamber with low frequency RF power of at least about 100 watts;  
   forming a dielectric layer over the SiOC layer.    
     
     
         31 . The method of  claim 30 , wherein the process of forming the SiOC etch stop layer is a non-He process.  
     
     
         32 . The method of  claim 30 , wherein the underlying layer is a SiC layer.  
     
     
         33 . The method of  claim 30 , wherein a flow rate of the 3MS flowing is about 100 sccm.  
     
     
         34 . The method of  claim 30 , wherein a flow rate of the CO 2  flowing is about 350 sccm.  
     
     
         35 . The method of  claim 30 , wherein the process of forming the SiOC layer further comprises: 
 heating the reaction chamber to a temperature of about 350° C.; and    energizing the reaction chamber with high frequency RF power of at about 400 watts.    
     
     
         36 . A semiconductor device comprising: 
 a layer of silicon carbide (SiC) material formed on an underlying layer;    a layer of SiOC material formed on the SiC layer, wherein the SiOC layer is capable of passing an electron migration test having conditions of about 300° C. with a J stress of about 2×10 6  A/cm 2  and capable of passing a stress migration test having conditions of about 175° C. for about 500 hours;    a dielectric layer formed on the SiOC layer; and    a conductor extending through the dielectric layer, the SiOC layer, and the SiC layer.    
     
     
         37 . The semiconductor device of  claim 36 , wherein the SiC material has a current leakage of less than about 1.0×10 −6  amps per square centimeter at an electric field of about 2 megavolts per centimeter.