Dynamically configurable clocking scheme for demand based resource sharing with multiple clock crossing domains

Abstract

A first clock signal having a first frequency is applied to drive a first module. A second clock signal having a second frequency is applied to drive a second module. The second frequency is different from the first frequency. A third clock signal is selectively applied with a frequency substantially the same as the first frequency to drive at least one portion of a resource to allow the first module to access the one portion of the resource. The third clock signal is selectively applied with a frequency substantially the same as the second frequency to drive at least the one portion of the resource to allow the second module to access the one portion of the resource.

What is claimed is:  
     
         1 . A method comprising: 
 applying a first clock signal having a first frequency to drive a first module;    applying a second clock signal having a second frequency to drive a second module, wherein the second frequency is different from the first frequency; and    selectively applying a third clock signal with a frequency substantially the same as the first frequency to drive at least one portion of a resource to allow the first module to access the one portion of the resource and with a frequency substantially the same as the second frequency to drive at least the one portion of the resource to allow the second module to access the one portion of the resource.    
     
     
         2 . The method of  claim 1 , comprising applying a fourth clock signal with a frequency substantially the same as the first frequency to drive at least another portion of the resource to allow the first module to access the other portion.  
     
     
         3 . The method of  claim 2 , wherein the selectively applying comprises applying the third clock signal with a frequency substantially the same as the second frequency to drive at least the one portion of the resource while the fourth clock signal is applied to drive at least the other portion of the resource.  
     
     
         4 . The method of  claim 1 , comprising halting the first clock signal while applying the third clock signal with a frequency substantially the same as the second frequency to drive at least the one portion of the resource.  
     
     
         5 . An apparatus comprising: 
 a resource comprising at least one portion;    a first module to access at least the one portion of the resource;    a second module to access at least the one portion of the resource; and    clocking circuitry coupled to drive the first module with a first clock signal having a first frequency, coupled to drive the second module with a second clock signal having a second frequency different from the first frequency, and coupled to drive at least the one portion of the resource selectively with a third clock signal with a frequency substantially the same as the first frequency and with a frequency substantially the same as the second frequency.    
     
     
         6 . The apparatus of  claim 5 , wherein the resource comprises at least the one portion and another portion; and 
 wherein the clocking circuitry is coupled to drive at least the other portion of the resource with a fourth clock signal with a frequency substantially the same as the first frequency.    
     
     
         7 . The apparatus of  claim 6 , wherein the clocking circuitry drives at least the one portion of the resource with the third clock signal with a frequency substantially the same as the second frequency while driving at least the other portion of the resource with the fourth clock signal.  
     
     
         8 . The apparatus of  claim 5 , wherein the clocking circuitry halts the first clock signal while driving at least the one portion of the resource with the third clock signal with a frequency substantially the same as the second frequency.  
     
     
         9 . The apparatus of  claim 5 , wherein the clocking circuitry comprises a multiplexer to output the first clock signal or the second clock signal selectively as the third clock signal to at least the one portion of the resource.  
     
     
         10 . The apparatus of  claim 5 , wherein the clocking circuitry comprises a plurality of multiplexers each to output the first clock signal or the second clock signal selectively as the third clock signal to a respective clock tap of the resource.  
     
     
         11 . The apparatus of  claim 5 , wherein the clocking circuitry comprises a first phase locked loop to generate the first clock signal and a second phase locked loop to generate the second clock signal.  
     
     
         12 . The apparatus of  claim 5 , wherein the first module comprises a processor and the second module comprises a graphics engine.  
     
     
         13 . The apparatus of  claim 5 , wherein the resource comprises a memory.  
     
     
         14 . The apparatus of  claim 5 , wherein the first module, the second module, and the resource are integrated on one chip.  
     
     
         15 . An integrated circuit chip comprising: 
 a cache memory comprising at least one portion;    a processor to access at least the one portion of the cache memory;    a graphics engine to access at least the one portion of the cache memory; and    clocking circuitry coupled to drive the processor with a first clock signal having a first frequency, coupled to drive the graphics engine with a second clock signal having a second frequency different from the first frequency, and coupled to drive at least the one portion of the cache memory selectively with a third clock signal with a frequency substantially the same as the first frequency and with a frequency substantially the same as the second frequency.    
     
     
         16 . The integrated circuit chip of  claim 15 , wherein the cache memory comprises at least the one portion and another portion; and 
 wherein the clocking circuitry is coupled to drive at least the other portion of the cache memory with a fourth clock signal with a frequency substantially the same as the first frequency.    
     
     
         17 . The integrated circuit chip of  claim 16 , wherein the clocking circuitry drives at least the one portion of the cache memory with the third clock signal with a frequency substantially the same as the second frequency while driving at least the other portion of the cache memory with the fourth clock signal.  
     
     
         18 . The integrated circuit chip of  claim 15 , wherein the clocking circuitry halts the first clock signal while driving at least the one portion of the cache memory with the third clock signal with a frequency substantially the same as the second frequency.  
     
     
         19 . The integrated circuit chip of  claim 15 , wherein the clocking circuitry comprises a multiplexer to output the first clock signal or the second clock signal selectively as the third clock signal to at least the one portion of the cache memory.  
     
     
         20 . The integrated circuit chip of  claim 15 , wherein the clocking circuitry comprises a plurality of multiplexers each to output the first clock signal or the second clock signal selectively as the third clock signal to a respective clock tap of the cache memory.  
     
     
         21 . The integrated circuit chip of  claim 15 , wherein the clocking circuitry comprises a first phase locked loop to generate the first clock signal and a second phase locked loop to generate the second clock signal.  
     
     
         22 . A computer system comprising: 
 (a) a main memory;    (b) a system clock; and    (c) an integrated circuit chip comprising: 
 (i) a cache memory comprising at least one portion,  
 (ii) a processor to access at least the one portion of the cache memory,  
 (iii) a graphics engine to access at least the one portion of the cache memory,  
 (iv) clocking circuitry coupled to the system clock, the clocking circuitry coupled to drive the processor with a first clock signal having a first frequency, coupled to drive the graphics engine with a second clock signal having a second frequency different from the first frequency, and coupled to drive at least the one portion of the cache memory selectively with a third clock signal with a frequency substantially the same as the first frequency and with a frequency substantially the same as the second frequency, and  
 (v) a memory controller coupled to the processor, to the graphics engine, and to the main memory to control access to the main memory.  
   
     
     
         23 . The computer system of  claim 22 , wherein the cache memory comprises at least the one portion and another portion; and 
 wherein the clocking circuitry is coupled to drive at least the other portion of the cache memory with a fourth clock signal with a frequency substantially the same as the first frequency.    
     
     
         24 . The computer system of  claim 22 , wherein the clocking circuitry comprises a multiplexer to output the first clock signal or the second clock signal selectively as the third clock signal to at least the one portion of the cache memory.  
     
     
         25 . An apparatus comprising: 
 a resource comprising at least one portion;    a first module to access at least the one portion of the resource;    a second module to access at least the one portion of the resource;    clocking circuitry coupled to drive the first module with a first clock signal having a first frequency, coupled to drive the second module with a second clock signal having a second frequency different from the first frequency, and coupled to drive at least the one portion of the resource selectively with a third clock signal with a frequency substantially the same as the first frequency and with a third frequency different from the first frequency and from the second frequency; and    clock crossing circuitry coupled to the second module and to the resource to allow the second module to access the resource while the clocking circuitry drives the resource with the third clock signal with the third frequency.    
     
     
         26 . The apparatus of  claim 25 , wherein the resource comprises at least the one portion and another portion; and 
 wherein the clocking circuitry is coupled to drive at least the other portion of the resource with a fourth clock signal with a frequency substantially the same as the first frequency.    
     
     
         27 . The apparatus of  claim 26 , wherein the clocking circuitry drives at least the one portion of the resource with the third clock signal with the third frequency while driving at least the other portion of the cache memory with the fourth clock signal.  
     
     
         28 . The apparatus of  claim 25 , wherein the clocking circuitry halts the first clock signal while driving at least the one portion of the resource with the third clock signal with the third frequency.  
     
     
         29 . The apparatus of  claim 25 , wherein the clocking circuitry comprises a multiplexer to output the first clock signal or another clock signal having the third frequency selectively as the third clock signal to at least the one portion of the resource.  
     
     
         30 . The apparatus of  claim 25 , wherein the first module comprises a processor, the second module comprises a graphics engine, and the resource comprises a memory; and 
 wherein the first module, the second module, and the resource are integrated on one chip.