Implementation of multiple flip flops as a standard cell using novel clock generation scheme

Abstract

Scan chain routing efficiency is improved in an integrated circuit (IC) such as an application specific integrated circuit (ASIC) by defining flip flop groupings prior to place and route. A flip flop grouping specifies the arrangement of multiple flip flops and the scan chain routing through those flip flops. The predetermined flip flop arrangement of the flip flop grouping then prevents undesirable flip flop placements during place and route. The flip flop grouping therefore minimizes the layout impacts of scan insertion while simplifying the place and route process. Different flip flop groupings can be used in a single IC design, and flip flop groupings can be combined with individual flip flops in the IC layout. A flip flop grouping can include control logic for the flip flops. Clock gating logic can be offloaded from the flip flops into the control logic to further improve layout efficiency.

1 . A method for creating an integrated circuit (IC), the method comprising: 
 defining a first flip flop grouping comprising a first plurality of flip flops in a first specified physical arrangement, each of the first plurality of flip flops having a data output terminal and a test input terminal, the first plurality of flip flops forming a daisy chain from a first flip flop to a second flip flop by connecting the data output terminal to the test input terminal of successive flip flops; and    placing a first instance of the first flip flop grouping in the IC.    
     
     
         2 . The method of  claim 1 , further comprising adding the first flip flop grouping as a single entity cell to a cell library.  
     
     
         3 . The method of  claim 1 , wherein the IC comprises an individual flip flop comprising a data output terminal and a test input terminal, the method further comprising connecting the data output terminal of the second flip flop of the first instance of the first flip flop grouping to the test input terminal of the individual flip flop.  
     
     
         4 . The method of  claim 1 , wherein the IC comprises an individual flip flop comprising a data output terminal and a test input terminal, the method further comprising connecting the data output terminal of the individual flip flop to the test input terminal of the first flip flop of the first instance. of the first flip flop grouping.  
     
     
         5 . The method of  claim 1 , further comprising: 
 placing a second instance of the first flip flop grouping in the IC; and    connecting the data output terminal of the second flip flop of the first instance to the test input terminal of the first flip flop of the second instance.    
     
     
         6 . The method of  claim 1 , further comprising: 
 defining a second flip flop grouping comprising a second plurality of flip flops in a second specified physical arrangement, each of the second plurality of flip flops having a data output terminal and a test input terminal, the second plurality of flip flops forming a daisy chain between a third flip flop and a fourth flip flop by connecting the data output terminal to the test input terminal of successive flip flops;    placing a first instance of the second flip flop grouping in the IC as a single entity; and    connecting the data output terminal of the second flip flop of the first instance of the first flip flop grouping to the test input terminal of the third flip flop of the first instance of the second flip flop grouping.    
     
     
         7 . The method of  claim 6 , wherein the second plurality is different from the first plurality.  
     
     
         8 . The method of  claim 1 , wherein defining the first flip flop grouping comprises incorporating clock gating logic into the first flip flop grouping.  
     
     
         9 . A single entity cell in a cell library, the single entity cell comprising: 
 a plurality of flip flops, each of the flip flops having a data output terminal and a test input terminal, the plurality of flip flops being arranged in a daisy chain from a first flip flop to a last flip flop by connecting the data output terminal and the test input terminal of successive flip flops;    a test input data terminal coupled to the test input terminal of the first flip flop; and    a test data output terminal coupled to the data output terminal of the last flip flop.    
     
     
         10 . The single entity cell of  claim 9 , further comprising control logic for controlling the behavior of the plurality of flip flops.  
     
     
         11 . The single entity cell of  claim 10 , wherein the plurality of flip flops is arranged to surround the control logic.  
     
     
         12 . The single entity cell of  claim 10 , wherein the control logic includes clock gating logic for the plurality of flip flops.  
     
     
         13 . The single entity cell of  claim 12 , wherein the control logic comprises a clock control circuit coupled to receive a data enable signal, a test enable signal, and a system clock signal, the clock control circuit generating a local clock signal only when the data enable signal or the test enable signal is asserted, the local clock signal being coupled to the plurality of flip flops.  
     
     
         14 . The single entity cell of  claim 13 , wherein each of the plurality of flip flops includes a data input terminal, and wherein the control logic further comprises an operational control circuit coupled to receive the data enable signal, the test enable signal, and the system clock signal, wherein the operation control circuit generates a data control signal when the data enable signal is asserted, the data control signal instructing each of the plurality of flip flops to latch input data from the data input terminal in response to the local clock signal, and wherein the operation control circuit generates a test control signal when the test enable signal is asserted, the test control signal instructing each of the plurality of flip flops to latch test data from the test input terminal.  
     
     
         15 . The single entity cell of  claim 14 , wherein the control logic further comprises a reset control circuit coupled to receive a reset signal, wherein the reset control circuit generates a reset control signal when the reset signal is asserted, the reset control signal causing each of the plurality of flip flops to be reset to a specified state.  
     
     
         16 . The single entity cell of  claim 15 , wherein each of the plurality of flip flops further comprises: 
 a master latch; and    a slave latch, the reset control signal comprising a master reset signal and a slave reset signal, the master reset signal setting the master latch to a first state, and the slave reset signal setting the slave latch to a second state, the first state and the second state placing the flip flop in specified state.    
     
     
         17 . The single entity cell of  claim 16 , wherein each of the plurality of flip flops further comprises: 
 a data input circuit including a first inverter connected between the data input terminal and a first complementary metal-oxide-semiconductor (CMOS) pass gate, the first CMOS pass gate being configured to turn on in response to the local clock signal when the data enable signal is asserted, the first CMOS pass gate having a first output terminal connected to the master latch; and    a test input circuit including a second inverter connected between the test input terminal and a second CMOS pass gate, the second CMOS pass gate being configured to turn on in response to the local clock signal when the test enable signal is asserted, the second CMOS pass gate having a second output terminal connected to the master latch.    
     
     
         18 . An integrated circuit (IC) including a first flip flop grouping, the first flip flop grouping comprising: 
 a first plurality of flip flops, the first plurality of flip flops being daisy chained as a first portion of a scan chain, the first plurality of flip flops having a first predetermined arrangement relative to one another; and    a first control logic circuit comprising clock gating logic for each of the first plurality of flip flops, the first control logic circuit having a second predetermined arrangement relative to the first plurality of flip flops.    
     
     
         19 . The IC of  claim 18 , further including a second flip flop grouping, the second flip flop grouping comprising: 
 a second plurality of flip flops, the second plurality being equal to the first plurality, the second plurality of flip flops being daisy chained as a second portion of the scan chain, the second plurality of flip flops having the first predetermined arrangement relative to one another; and    a second control logic circuit comprising clock gating logic for each of the second plurality of flip flops, the second control logic circuit having the second predetermined arrangement relative to the second plurality of flip flops.    
     
     
         20 . The IC of  claim 18 , wherein the first control logic circuit includes a clock control circuit, the clock control circuit being coupled to receive an input enable signal, a test enable signal, and a system clock signal, the clock control circuit generating a local clock signal from the system clock signal when either the input enable signal or the test enable signal is asserted, the first plurality of flip flops being clocked by the local clock signal.  
     
     
         21 . The IC of  claim 20 , wherein the first control logic circuit further comprises test control logic, the test control logic being coupled to receive the test enable signal and the system clock signal, the test control logic providing a test control signal to the first plurality of flip flops when the test enable signal is asserted, the test control signal instructing the first plurality of flip flops to load test data according to the local clock signal  
     
     
         22 . The IC of  claim 21 , wherein the test control logic is further coupled to receive the input enable signal, the test control logic providing an input control signal to the first plurality of flip flops when the input enable signal is asserted and the test enable signal is deasserted, the input control signal instructing the first plurality of flip flops to load non-test data according to the local clock signal.  
     
     
         23 . The IC of  claim 22 , wherein each of the first plurality of flip flops comprises: 
 a master latch;    a slave latch connected to the master latch in a flip flop configuration;    a data input circuit having a data input terminal, the data input circuit being configured to provide data at the data input terminal to the master latch in response to the input control signal; and    a test input circuit having a test input terminal, the test input circuit being configured to provide data at the test input terminal to the master latch in response to the test control signal.    
     
     
         24 . The IC of  claim 18 , wherein the IC is an application specific integrated circuit (ASIC).