Reduced architecture for multibranch feedforward power amplifier linearizers

Abstract

An amplifier linearizer circuit has a signal cancellation circuit including a signal adjuster having M branch signals (M≧1), and a distortion cancellation circuit including a signal adjuster having N branch signals (N≧1). The linearizer has a controller for adaptively controlling the M-branch and N-branch signal adjusters. The controller has only one monitor receiver to monitor the M branch signals and only one monitor receiver to monitor the N branch signals.

What is claimed is:  
     
         1 . An amplifier linearizer comprising: 
 a signal cancellation circuit including a signal adjuster having M branch signals (M≧1); and    a controller for adaptively controlling said M-branch signal adjuster, said controller including only one monitor receiver to monitor the M branch signals.    
     
     
         2 . An amplifier linearizer comprising: 
 a distortion cancellation circuit including a signal adjuster having N branch signals (N≧1); and    a controller for adaptively controlling said N-branch signal adjuster, said controller including only one monitor receiver to monitor the N branch signals.    
     
     
         3 . An amplifier linearizer comprising: 
 a signal cancellation circuit including a signal adjuster having M branch signals (M≧1);    a distortion cancellation circuit including a signal adjuster having N branch signals (N≧1); and    a controller for adaptively controlling said M-branch signal adjuster and said N-branch signal adjuster, said controller including only one monitor receiver to monitor the M branch signals and only one monitor receiver to monitor the N branch signals.    
     
     
         4 . An amplifier linearizer comprising: 
 a signal cancellation circuit including a signal adjuster having M branch signals (M≧1); and    a local oscillator for producing a plurality of pilot tones to guide adaptation of said signal adjuster.    
     
     
         5 . A feedforward amplifier linearizer comprising: 
 a signal cancellation circuit; and    a distortion cancellation circuit,    wherein the signal cancellation circuit and distortion cancellation circuit are configured such that the linearizer achieves approximately 35 dB of distortion cancellation over a 15 MHz bandwidth.    
     
     
         6 . A feedforward amplifier linearizer according to  claim 5 , wherein the linearizer instead achieves approximately 35 dB of distortion cancellation over a 25 MHz bandwidth.  
     
     
         7 . A feedforward amplifier linearizer according to  claim 5 , wherein the linearizer instead achieves approximately 25 dB of distortion cancellation over a 60 MHz bandwidth.  
     
     
         8 . A feedforward amplifier linearizer according to  claim 5 , wherein the linearizer instead achieves approximately 20 dB of distortion cancellation over a 75 MHz bandwidth.