US2004108553A1PendingUtilityA1
Semiconductor device and process for same
Est. expiryJan 18, 2021(expired)· nominal 20-yr term from priority
H10D 84/0188H10D 84/0177H10D 84/0174H10D 84/0186H10D 84/038
35
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Claims
Abstract
A dual gate type CMOS device according to the present invention includes a silicon substrate having a trench in the main surface and a gate electrode including a polysilicon film and a tungsten silicide film formed above the main surface via a gate insulating film. The polysilicon film has a first part into which p type impurities are doped, a second part into which n type impurities are doped and a connection part which connects the first part and the second part within the trench, and part of the tungsten silicide film located above the connection part is removed.
Claims
exact text as granted — not AI-modifiedWhat is claimed is:
1 . A semiconductor device comprising:
a semiconductor substrate having a trench at the main surface; and a gate electrode which is formed on said main surface with a gate insulating film interposed and which includes a silicon film and a metal-based conductive film, wherein said silicon film has a first part into which impurities of a first conductive type are doped, a second part into which impurities of a second conductive type are doped and a connection part which connects said first part and said second part within said trench; and part of said metal-based conductive film located above said connection part is removed.
2 . The semiconductor device according to claim 1 , wherein:
a recess is provided above said trench reaching said connection part, penetrating through said metal-based conductive film; and an insulating film is filled in into said recess.
3 . The semiconductor device according to claim 1 , wherein:
said trench is formed in an element isolation region; said connection part is formed within said trench with a underlying insulating film interposed; and the thickness of said underlying insulating film is larger than the thickness of said gate insulating film.
4 . The semiconductor device according to claim 3 , wherein the minimum width of the aperture part of said trench surrounded by said underlying insulating film is two times, or less, as large as the thickness of said silicon film.
5 . A process for a semiconductor device comprising:
the step of forming a trench isolation region at a main surface of a semiconductor substrate; the step of forming, on said main surface, a silicon film having a first part into which impurities of a first conductive type are doped and a second part into which impurities of a second conductive type are doped, a metal-based conductive film and a first insulating film; the step of forming gate electrodes by patterning said first insulating film, metal-based conductive film and silicon film; the step of forming a second insulating film so as to cover said first insulating film; the step of forming a first mask film on said second insulating film; the step of forming a first sidewall insulating film on the sidewalls of said gate electrodes by etching said second insulating film using said first mask film and of selectively exposing the surface of said first insulating film; the step of forming a second mask film on the surface of said first insulating film so as to expose part of the surface of said first insulating film, which is located above said trench isolation region, and said second insulating film; and the step of forming a second sidewall insulating film on the sidewalls of said gate electrodes by etching said second insulating film using said second mask film and of forming a recess reaching to said silicon film by etching said first insulating film and metal-based conductive film located above said trench isolation region.
6 . The process for a semiconductor device according to claim 5 comprising:
the step of forming a pair of first impurity regions which become the source and drain of a first MOS (metal oxide semiconductor) transistor by injecting impurities of the first conductive type into the main surface of said semiconductor substrate by using said first mask film, said first sidewall insulating film and the first part of said gate electrodes as a mask; and
the step of forming a pair of second impurity regions which become the source and drain of a second MOS (metal oxide semiconductor) transistor by injecting impurities of the second conductive type into the main surface of said semiconductor substrate by using said second mask film, said second sidewall insulating film and the second part of said gate electrodes as a mask.
7 . A process for a semiconductor device comprising:
the step of forming a trench for element isolation at a main surface of a semiconductor substrate; the step of forming an underlying insulating film on the surface within said trench; the step of forming, on said main surface, a silicon film having a first part into which impurities of a first conductive type are doped and a second part into which impurities of a second conductive type are doped and of forming a connection part of said first and second parts in said silicon film within said trench with said underlying insulating film; the step of forming a metal-based conductive film and an insulating film on said silicon film; the step of forming, on said insulating film, a mask film having an aperture above said trench; and the step of forming gate electrodes by patterning said insulating film, metal-based conductive film and silicon film by using said mask film and of forming a recess above said trench to reach said connection part.
8 . The process for a semiconductor device according to claim 7 , wherein said process of forming said underlying insulating film includes:
the step of forming a buried insulating film which is filled in into said trench; the step of forming a first aperture part reaching to the bottom surface of said trench, penetrating through said buried insulating film; and the step of forming a bottom part insulating film which covers the exposed bottom surface of said trench so as to form a second aperture part above said trench.Join the waitlist — get patent alerts
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