US2004104491A1PendingUtilityA1

Wafer back side coating to balance stress from passivation layer on front of wafer and be used as a die attach adhesive

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Priority: Feb 25, 2002Filed: Nov 12, 2003Published: Jun 3, 2004
Est. expiryFeb 25, 2022(expired)· nominal 20-yr term from priority
Inventors:Michael ConnellTongbi Jiang
H10W 72/0198H10W 42/121H10P 54/00
42
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Claims

Abstract

A method and apparatus for balancing layer-caused compressive or tensile stress in a semiconductor die, die wafer or similar substrate uses a stress-balancing layer (SBL) attached to the opposite side from the stress-causing layer before the die or wafer is significantly warped. The SBL may also serve as, or support, an adhesive layer for die attach and be of a markable material for an enhanced marking method.

Claims

exact text as granted — not AI-modified
What is claimed is:  
     
         1 . A semiconductor die, comprising: 
 a semiconductor substrate having a front side and a back side;    an integrated circuit on a portion of said front side;    a passivation layer covering a portion of said integrated circuit; and    a stress-balancing layer covering at least a portion of said back side.    
     
     
         2 . A semiconductor die in accordance with  claim 1 , wherein said stress-balancing layer comprises one of a single component layer, a substantially homogeneous mixture of a strong material in a matrix material, a heterogeneous composite of particles of a strong material in a matrix material, and a tape with rigidity in the X-Y plane.  
     
     
         3 . A semiconductor die in accordance with  claim 1 , wherein said stress-balancing layer comprises an adhesive material.  
     
     
         4 . A semiconductor die in accordance with  claim 1 , wherein said stress-balancing layer comprises a layer for laser-marking.  
     
     
         5 . A semiconductor die in accordance with  claim 1 , further comprising an adhesive layer attached to said stress-balancing layer.  
     
     
         6 . A nonwarp semiconductor die in accordance with  claim 5 , wherein said adhesive layer comprises a layer of material for laser-marking.  
     
     
         7 . A nonwarp semiconductor die, comprising: 
 a semiconductor substrate having a front side, a back side, and a low ratio of height to a horizontal dimension;    an integrated circuit on said front side;    a passivation layer covering a portion of said integrated circuit exerting a stress on said substrate front side; and    a stress-balancing layer covering at least a portion of said back side, said stress-balancing layer for balancing a portion of said front side stress with a generally equivalent back side stress.    
     
     
         8 . A nonwarp semiconductor die in accordance with  claim 7 , wherein said stress-balancing layer comprises one of a single component layer, a substantially homogeneous mixture of a strong material in a matrix material, a heterogeneous composite of particles of a strong material in a matrix material, and a tape with rigidity in the X-Y plane.  
     
     
         9 . A nonwarp semiconductor die in accordance with  claim 7 , wherein said stress-balancing layer comprises an adhesive material.  
     
     
         10 . A nonwarp semiconductor die in accordance with  claim 9 , wherein said stress-balancing layer comprises a layer of material for laser-marking.  
     
     
         11 . A nonwarp semiconductor die in accordance with  claim 7 , further comprising an adhesive layer attached to said stress-balancing layer.  
     
     
         12 . A nonwarp semiconductor die in accordance with  claim 11 , wherein said adhesive layer for laser-marking comprises a layer of material for laser-marking.  
     
     
         13 . A semiconductor die, comprising: 
 a semiconductor substrate having a front side having an integrated circuit on a portion thereof and a back side;    a passivation layer covering a portion of said integrated circuit; and    a stress-balancing layer covering at least a portion of said back side.    
     
     
         14 . The semiconductor die of  claim 13 , wherein said stress-balancing layer comprises one of a single component layer, a substantially homogeneous mixture of a strong material in a matrix material, a heterogeneous composite of particles of a strong material in a matrix material, and a tape with rigidity in the X-Y plane.  
     
     
         15 . The semiconductor die of  claim 13 , wherein said stress-balancing layer comprises an adhesive material.  
     
     
         16 . The semiconductor die of  claim 13 , wherein said stress-balancing layer comprises a layer for laser-marking.  
     
     
         17 . The semiconductor die of  claim 13 , further comprising an adhesive layer attached to said stress-balancing layer.  
     
     
         18 . The semiconductor die of  claim 17 , wherein said adhesive layer comprises a layer of material for laser-marking.  
     
     
         19 . A reduced stress semiconductor die, comprising: 
 a semiconductor substrate having a front side, a back side, and a low ratio of the height of the semiconductor substrate to a horizontal dimension of the semiconductor substrate;    an integrated circuit on said front side of the semiconductor substrate;    a passivation layer covering a portion of said integrated circuit causing a force acting on a portion of said substrate front side; and    a force-balancing layer covering at least a portion of said back side, said force-balancing layer for balancing a portion of said force on said front side.    
     
     
         20 . The semiconductor die of  claim 19 , wherein said force-balancing layer comprises one of a single component layer, a substantially homogeneous mixture of a strong material in a matrix material, a heterogeneous composite of particles of a strong material in a matrix material, and a tape with rigidity in the X-Y plane.  
     
     
         21 . The semiconductor die of  claim 19 , wherein said stress-balancing layer comprises an adhesive material.  
     
     
         22 . The semiconductor die of  claim 21 , wherein said stress-balancing layer comprises a layer of material for laser-marking.  
     
     
         23 . The semiconductor die of  claim 19 , further comprising an adhesive layer attached to said stress-balancing layer.  
     
     
         24 . The semiconductor die of  claim 23 , wherein said adhesive layer for laser-marking comprises a layer of material for laser-marking.

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