US2004104448A1PendingUtilityA1

Integrated circuit with a strongly-conductive buried layer

Priority: Oct 3, 2002Filed: Oct 3, 2003Published: Jun 3, 2004
Est. expiryOct 3, 2022(expired)· nominal 20-yr term from priority
H10D 64/231H10D 62/137H10D 10/051H10D 10/00
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Claims

Abstract

An integrated circuit including a buried layer of determined conductivity type in a plane substantially parallel to the plane of a main circuit surface, in which the median portion of this buried layer is filled with a metal-type material.

Claims

exact text as granted — not AI-modified
What is claimed is:  
     
         1 . An integrated circuit comprising a buried layer of determined conductivity type in a plane substantially parallel to the plane of a main circuit surface, wherein a median portion of said buried layer is filled with a metal-type material.  
     
     
         2 . The integrated circuit of  claim 1 , wherein the buried layer is a sub-collector layer of a bipolar transistor.  
     
     
         3 . The integrated circuit of  claim 1 , wherein the metal-type material is titanium nitride.  
     
     
         4 . A method for forming a buried layer in a semiconductor substrate of an integrated circuit, comprising the steps of: 
 providing, at the location where the buried layer is to be formed, a layer portion made of a material selectively etchable with respect to the rest of the semiconductor material,    doping the semiconductor substrate according to a chosen conductivity type on either side of said layer portion,    digging an opening extending from the integrated circuit surface to said layer portion,    removing said layer portion by isotropic etch, and    filling the cavity thus formed with a metal-type material.    
     
     
         5 . The method of  claim 4 , wherein the layer portion is delimited by an insulating wall.  
     
     
         6 . The method of  claim 4 , wherein the layer portion is a silicon-germanium region formed by epitaxy on a silicon substrate and itself covered with a silicon epitaxial layer.  
     
     
         7 . The method of  claim 4 , wherein the layer portion is a silicon oxide region, formed on a silicon substrate and coated with a silicon layer.  
     
     
         8 . The method of  claim 4 , wherein the layer portion is a hollowed region formed in advance in the semiconductor substrate.

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