Method of manufacturing silicon wafer

Abstract

A method of manufacturing a silicon wafer including the step of flattening fine roughness existing on a side face of a silicon block or a silicon stack used for manufacturing the silicon wafer.

What is claimed is:  
     
         1 . A method of manufacturing a silicon wafer comprising the step of flattening fine roughness existing on a side face of a silicon block or a silicon stack used for manufacturing the silicon wafer.  
     
     
         2 . A method according to  claim 1 , wherein the step of flattening comprises spraying a mixture of abrasive grains and a medium on the side face of the silicon block or the silicon stack, shifting closer or contacting a polishing member to or with the side face to be polished, and moving the silicon block or the silicon stack relatively to the polishing member in the presence of the abrasive grains so that the side face of the silicon block or the silicon stack is mechanically and physically polished.  
     
     
         3 . A method according to  claim 1 , wherein the step of flattening comprises spraying a medium on the side face of the silicon block or the silicon stack, shifting closer or contacting a polishing member having abrasive grains on its surface and/or in the inside thereof to or with the side face to be polished, and moving the silicon block or the silicon stack relatively to the polishing member so that the side face of the silicon block or the silicon stack is mechanically and physically polished.  
     
     
         4 . A method according to claims  2  or  3 , wherein the polishing is carried out while spraying the mixture of the abrasive grains and the medium or the medium solely.  
     
     
         5 . A method according to any one of  claims 1  to  4 , wherein the flattened side face of the silicon block or the silicon stack has surface roughness Ry of 8 μm or less.  
     
     
         6 . A method according to  claim 5 , wherein the flattened side face of the silicon block or the silicon stack has surface roughness Ry of 6 μm or less.  
     
     
         7 . A method according to any one of  claims 1  to  6 , wherein a section of the silicon block or the silicon stack is constructed of four main lines, the lines forming an angle of about 90° with adjacent lines, respectively.