Method for forming landing plug in semiconductor device

Abstract

The present invention relates to a method for forming a landing plug capable of securing a low resistance by employing a selective epitaxial growth technique to meet demands of high-integration and high-speed in a semiconductor device. The method includes the steps of: forming an inter-layer insulation layer on a substrate; forming a contact hole by etching the inter-layer insulation layer until exposing a partial portion of the substrate; forming a first conductive layer with a predetermined thickness inside of the contact hole, the first conductive layer being made of a silicon layer; forming a second conductive layer on the inter-layer insulation layer in such a manner of being buried into the contact hole in which the silicon layer is formed; and performing a blanket etch process to the second conductive layer until exposing surfaces of the inter-layer insulation layer and the hard mask so that a landing plug is formed.

What is claimed is:  
     
         1 . A method for forming a landing plug, comprising the steps of: 
 forming an inter-layer insulation layer on a substrate;    forming a contact hole by etching the inter-layer insulation layer until exposing a partial portion of the substrate;    forming a first conductive layer with a predetermined thickness inside of the contact hole, the first conductive layer being made of a silicon layer;    forming a second conductive layer on the inter-layer insulation layer in such a manner of being buried into the contact hole in which the silicon layer is formed; and    performing a blanket etch process to the second conductive layer until exposing surfaces of the inter-layer insulation layer and the hard mask so that a landing plug is formed.    
     
     
         2 . The method as recited in  claim 1 , wherein the second conductive layer is made of any material selected from a group consisting of WSi x , TiSi x , CoSi x , CrSi x , NiSi x , TaSi x , HfSi x , ZrSi x , FeSi x , YSi x  and MoSi x , and among these materials, the WSi x  is more preferable.  
     
     
         3 . The method as recited in  claim 2 , wherein the x indicating the number of atoms presenting in a molecule ranges from about 0.5 to about 2.5.  
     
     
         4 . The method as recited in  claim 2 , wherein the WSi x  layer has a thickness ranging from about 100 Å to about 2000 Å.  
     
     
         5 . The method as recited in  claim 1 , wherein the second conductive layer is formed by stacking the W layer and the WN x  layer.  
     
     
         6 . The method as recited in  claim 5 , wherein each of the W layer and the WN x  layer has a thickness in a range from about 20 Å to about 2000 Å.  
     
     
         7 . The method as recited in  claim 5 , wherein the WN x  layer is substituted with metal nitride containing any metal selected from a group consisting of Ta, Ti, Mo, Cr, Co, Hf and Zr.  
     
     
         8 . The method as recited in  claim 7 , wherein the x indicating the number of atoms presenting in the molecule of WN, ranges from about 0.1 to about 1.0.  
     
     
         9 . The method as recited in  claim 5 , wherein the WN x  layer is substituted with any layer selected from a group consisting of a WSi x N y  layer, a TaSi x N y  layer, a TiSi x N y  layer, a TiAl x N y  layer, a TaAl x N y  layer, a RuTi x N y  layer and a RuTa x N y  layer.  
     
     
         10 . The method as recited in  claim 9 , wherein each of the x and y indicating the number of atoms presenting in a molecule ranges from about 0.1 to about 4.0.  
     
     
         11 . The method as recited in  claim 5 , wherein the WN x  layer is substituted with a RuO x  layer or an IrO x  layer.  
     
     
         12 . The method as recited in  claim 11 , wherein the x indicating the number of atoms presenting in the molecule of WN x  ranges from about 0.1 to about 3.0.  
     
     
         13 . The method as recited in  claim 5 , wherein the W layer is substituted with any layer selected from a group consisting of a Ta layer, a Ti layer, a Mo layer, a Cr layer, a Co layer, a Hf layer, a Zr layer, a Ru layer, an Ir layer and a Pt layer.  
     
     
         14 . The method as recited in  claim 1 , wherein the second conductive layer is proceeded with an annealing process after the step of forming the second conductive layer or the step of performing the blanket etch process.  
     
     
         15 . The method as recited in  claim 14 , wherein the annealing process is carried out at a temperature ranging from about 600° C. to about 1000° C. for about 10 seconds to about 1 hour.  
     
     
         16 . The method as recited in  claim 1 , wherein the silicon layer is formed through a selective epitaxial growth (SEG) technique.  
     
     
         17 . The method as recited in  claim 16 , wherein the silicon layer has a thickness in a range from about 10 Å to about 2000 Å.