Semiconductor device and fabrication method thereof

Abstract

A bonding pad of a semiconductor device and a fabrication method thereof are disclosed. A semiconductor device having a pad formed by exposing a predetermined region of a metal line formed over a semiconductor substrate includes an alloy layer formed on the metal line exposed through the pad. The alloy layer is formed from a reaction between the metal line and a metal having a melting point less than or equal to 1000° C.

What is claimed is:  
     
         1 . A semiconductor device having a pad formed by exposing a predetermined region of a metal line formed over a semiconductor substrate, the semiconductor device comprising; 
 an alloy layer formed on the metal line exposed through the pad, wherein the alloy layer is formed from a reaction between the metal line and a metal having a melting point less than or equal to 1000° C.    
     
     
         2 . The semiconductor device of  claim 1 , wherein the metal line is made of copper.  
     
     
         3 . The semiconductor device of  claim 1 , wherein the metal having the melting point less than or equal to 1000° C. is selected from the group consisting of aluminum, lead, and silver.  
     
     
         4 . The semiconductor device of  claim 1 , wherein the thickness of the alloy layer is less than a thickness of the metal line.  
     
     
         5 . The semiconductor device of  claim 1 , wherein a protection layer made of one of silicon nitride and silicon oxynitride is formed on the metal line except where the pad is formed.  
     
     
         6 . The semiconductor device of  claim 2 , wherein the copper is filled in a via.  
     
     
         7 . The semiconductor device of  claim 6 , wherein a barrier metal is formed on an interface between the copper and the via made from a metal selected from the group consisting of Ti, Ta, TiN, and TaN having a thickness between 200 and 800 Å to prevent the diffusion of the copper out of the via.  
     
     
         8 . The semiconductor device of  claim 6 , wherein a width of the pad is less than a width of the via.  
     
     
         9 . A method of fabricating a semiconductor device comprising: 
 forming a via by etching a predetermined region of an insulating layer over a semiconductor substrate;    filling the via with a metal to form an outermost metal line;    forming a reaction layer on the outermost metal line and the insulating layer, wherein the reaction layer has a melting point of less than or equal to 1000° C.; and    performing a heat treatment process to react the reaction layer and the outermost metal line, thereby forming an alloy layer on a interface between the reaction layer and the outermost metal line.    
     
     
         10 . The method of  claim 9 , wherein the outermost metal line is made of copper.  
     
     
         11 . The method of  claim 9 , wherein the reaction layer is made of a material selected from the group consisting of aluminum, lead, and silver.  
     
     
         12 . The method of  claim 9 , wherein a physical vapor deposition process including a sputtering method is used to form the reaction layer at a temperature of 300° C. or less.  
     
     
         13 . The method of  claim 9 , wherein the reaction layer is deposited to a thickness that is less than a thickness of the outermost metal line.  
     
     
         14 . The method of  claim 9 , wherein the heat treatment process is performed at a temperature of 350˜450° C. for a duration of 10 to 60 minutes.  
     
     
         15 . The method of  claim 10 , wherein the copper is formed on a barrier metal layer after forming the barrier metal layer from a metal selected from the group consisting of Ti, Ta, TiN, and TaN having a thickness between 200 and 800 Å along inner walls of the via to prevent the diffusion of the copper out of the via.  
     
     
         16 . The method of  claim 9 , further comprising the steps of: 
 performing an anisotropic etching process until the insulating layer is exposed such that the alloy layer is left remaining within the via;    forming a protection layer on the insulating layer and the alloy layer; and    etching a predetermined region of the protection layer to form a pad that exposes a predetermined region of the alloy layer.    
     
     
         17 . The method of  claim 16 , wherein the protection layer is formed of one of silicon nitride and silicon oxynitride.  
     
     
         18 . The method of  claim 16 , wherein the predetermined region of the protection layer is etched to a width less than a width of the via to form the pad.  
     
     
         19 . The method of  claim 16 , wherein the anisotropic etching process is one of a chemical mechanical polishing process and an etch back process.  
     
     
         20 . The method of  claim 16 , further comprising a cleaning process that is performed after the anisotropic etching process, and a heat treatment process that is performed at a temperature of 250˜350° C. for a duration of 10 to 60 minutes after the cleaning process.