Method of decontaminating process chambers, methods of reducing defects in anti-reflective coatings, and resulting semiconductor structures

Abstract

A method for fabricating a substantially smooth-surfaced anti-reflective coating on a semiconductor device structure including generating a plasma from an inert gas in a process chamber in which the anti-reflective coating is to be deposited. The anti-reflective coating may include silicon, oxygen and nitrogen, and is preferably of the general formula Si x O y N z , where x equals 0.40 to 0.65, y equals 0.02 to 0.56 and z equals 0.05 to 0.33. Preferably, x+y+z equals one. The method may also include fabricating a silicon nitride layer over the anti-reflective coating. A semiconductor device comprising a silicon nitride layer over the anti-reflective coating including at most about 1¼ in-film particles per square millimeter of surface area particles or surface roughness features in the silicon nitride of about 120-150 nanometers. Accordingly, a mask that is subsequently formed over the silicon nitride layer has a substantially uniform thickness and is substantially distortion-free.

What is claimed is:  
     
         1 . A semiconductor device structure, comprising: 
 a first layer comprising anti-reflective material; and    a second layer comprising silicon nitride, located over said first layer, and including at most about 1¼ in-film particles per square millimeter of surface area.    
     
     
         2 . The semiconductor device structure of  claim 1 , wherein said anti-reflective material comprises silicon atoms and nitrogen atoms.  
     
     
         3 . The semiconductor device structure of  claim 2 , wherein said anti-reflective material further comprises oxygen atoms.  
     
     
         4 . The semiconductor device structure of  claim 1 , wherein said anti-reflective material comprises Si.sub.x O.sub.y N.sub.z, where x equals about 0.40 to about 0.65 times the sum of x, y, and z, y equals about 0.02 to about 0.56 times the sum of x, y, and z, and z equals about 0.05 to about 0.33 times the sum of x, y, and z.  
     
     
         5 . The semiconductor device structure of  claim 1 , wherein a surface of said first layer is substantially free of at least one of measurable particulates and surface roughness.  
     
     
         6 . The semiconductor device structure of  claim 1 , wherein said second layer includes at most about 1¼ of at least one of particles and surface roughness features of at least about 120 nm dimension per square millimeter of surface area.  
     
     
         7 . The semiconductor device structure of  claim 1 , wherein said second layer is formed on said first layer.  
     
     
         8 . A semiconductor device structure, comprising: 
 a first layer comprising anti-reflective material; and    a second layer comprising silicon nitride, located over said first layer, and including at most about 1¼ in-film particles per square millimeter of surface area.    
     
     
         9 . The semiconductor device structure of  claim 8 , wherein said anti-reflective material comprises silicon atoms and nitrogen atoms.  
     
     
         10 . The semiconductor device structure of  claim 9 , wherein said anti-reflective material further comprises oxygen atoms.  
     
     
         11 . The semiconductor device structure of  claim 8 , wherein said anti-reflective material comprises Si.sub.x O.sub.y N.sub.z, where x equals about 0.40 to about 0.65 times the sum of x, y, and z, y equals about 0.02 to about 0.56 times the sum of x, y, and z, and z equals about 0.05 to about 0.33 times the sum of x, y, and z.  
     
     
         12 . The semiconductor device structure of  claim 8 , wherein a surface of said first layer is substantially free of at least one of measurable particulates and surface roughness.  
     
     
         13 . The semiconductor device structure of  claim 8 , wherein said second layer includes at most about 1¼ of at least one of particles and surface roughness features of at least about 120 nm dimension per square millimeter of surface area.  
     
     
         14 . The semiconductor device structure of  claim 8 , wherein said second layer is formed on said first layer.