Test data generating system and method to test high-speed actual operation

Abstract

A test data generating system and method to conduct high-speed operation (actual operation) test of an LSI using a tester. The system converts existing simulation data to high-speed operation verifying test data which is formed to obtain a predetermined output expectation value after a clock signal is stopped for a predetermined period. The test data generating system includes a selecting device to select first output expectation values from simulation data and an inserting device to insert output expectation values, which are identical to a predetermined number of the first expectation values, after the first output expectation values. The system also inserts an input pattern, which is identical to a predetermined number of the input patterns, after the input pattern corresponding to the first output expectation value. A replacing device replaces the predetermined output expectation values of the simulation data with third output expectation values, and a setting device sets the first output expectation values to second output expectation values determined from the simulation data based on the predetermined number or the third output expectation values.

What is claimed is:  
     
         1 . A high speed test method to test a semiconductor device, comprising: 
 selecting a first output expectation value from simulation data, the first output expectation value corresponding to an input value;    inserting a predetermined number of output expectation values which are identical to the first output expectation value into the simulation data, after the first output expectation value;    inserting a predetermined number of input values, which are identical to the input value, into the simulation data after the input value corresponding to the first output expectation; and    carrying out the high speed test with the simulation data.    
     
     
         2 . A high speed test method With simulation data having output expectation values and input values, comprising: 
 selecting a first output expectation value from the simulation data, the first output expectation value corresponding to an input value;    inserting a predetermined number of output expectation values, which are identical to the first output expectation value, into the simulation data after the first output expectation value;    inserting a predetermined number of input values, which are identical to the input value, into the simulation data expectation after the input value corresponding to the first output expectation; and    carrying out the high speed test by using the inserted output expectation values and the inserted input values.    
     
     
         3 . The high speed test method as recited in  claim 1 , wherein the predetermined number is a number of cycles during which a clock signal is stopped.  
     
     
         4 . The high speed test method as recited in  claim 3 , wherein the number of cycles to stop the clock signal is determined based on capacitance of the elements forming a tester.  
     
     
         5 . The high speed test method as recited in  claim 1 , wherein the first output expectation value is selected for every predetermined cycle.  
     
     
         6 . The high speed test method as recited in  claim 2 , wherein the predetermined number is a number of cycles during which a clock signal is stopped.  
     
     
         7 . The high speed test method as recited in  claim 6 , wherein the number of cycles to stop the clock signal is determined based on capacitance of the elements forming a tester.  
     
     
         8 . The high speed test method as recited in  claim 2 , wherein the first output expectation value is selected for every predetermined cycle.