System for reordering sequenced based packet segments in a switching network

Abstract

System for reordering packet segments in a switching network. A system is provided for reordering packet segments in a packet switch network, wherein a plurality of source processors transmit the packet segments to a destination processor via one or more network fabrics. The system comprises encoder logic at each source processor that operates to associate a unique segment identifier with each of the packet segments before they are transmitted. A memory and map logic located at the destination processor operate to receive the packet segments, map the segment identifier associated with each of the packet segments to a memory region in the memory, and store each received packet at its respective memory region. A Dequeue processor coupled to the memory operates to determine when enough packet segments are stored in the memory to form a complete data frame and outputs that frame.

What is claimed is:  
     
         1 . A system for reordering packet segments in a packet switch network, wherein a plurality of source processors transmit the packet segments to a destination processor via one or more network fabrics, the system comprising: 
 encoder logic at each source processor that operates to associate a unique segment identifier with each of the packet segments before they are transmitted;    a memory located at the destination processor;    map logic at the destination processor that operates to receive the packet segments, map the segment identifier associated with each of the packet segments to a memory region in the memory, and store each received packet at its respective memory region; and    a Dequeue processor coupled to the memory and operable to determine when enough packet segments are stored in the memory to form a complete data frame, wherein the Dequeue processor operates to output the packet segments that form the complete data frame.    
     
     
         2 . The system of  claim 1 , wherein the memory regions are associated with the source processors, one memory region per source processor.  
     
     
         3 . The system of  claim 1 , wherein the map logic includes a map processor and map tables.  
     
     
         4 . The system of  claim 1 , wherein the segment identifier includes a source identifier and a segment identifier.  
     
     
         5 . The system of  claim 4 , wherein the segment identifier includes priority level indicator that is chosen from selected priority levels.  
     
     
         6 . The system of  claim 5 , wherein the one or more memory regions are associated with the source processors and the selected priority levels, and wherein the total number of memory regions is equal to the number of source processors times the number of selected priority levels.  
     
     
         7 . A method for reordering packet segments in a packet switch network, wherein a plurality of source processors transmit the packet segments to a destination processor via one or more network fabrics, the method comprising steps of: 
 including a segment identifier with each of the packet segments before they are transmitted from the source processors;    defining one or more memory regions in a memory located at the destination processor;    mapping the segment identifier associated with each received packet segment to a selected memory region, wherein the received packet segment is stored at the selected memory region;    updating a memory map;    identifying when enough packet segments have been received to form a complete data frame; and    outputting the complete data frame.    
     
     
         8 . The method of  claim 7 , wherein the step of including further comprises a step of including a priority level indicator with each of the packet segments before they are transmitted from the source processors, wherein the priority level indicator is chosen from selected priority levels.  
     
     
         9 . The method of  claim 8 , wherein the step of defining further comprises a step of defining the one or more memory regions so that the total number of memory regions is equal to the number of source processors times the number of selected priority levels.  
     
     
         10 . The method of  claim 7 , further comprising a step of including a new segment identifier with each of the packet segments before they are outputted by the destination processor.  
     
     
         11 . A destination processor for reordering packet segments in a packet switch network, wherein one or more source processors transmit the packet segments to the destination processor via one or more network fabrics, and wherein the packets are encoded with a unique segment identifier before transmission from the source processors, the destination processor comprising: 
 a memory;    map logic that operates to receive the packet segments, map the segment identifier associated with each of the packet segments to a memory region in the memory, and store each received packet at its respective memory region; and    a Dequeue processor coupled to the memory and operable to determine when enough packet segments are stored in the memory to form a complete data frame, wherein the Dequeue processor operates to output the complete data frame.    
     
     
         12 . The system of  claim 11 , wherein the memory regions are associated with the source processors, one memory region per source processor.  
     
     
         13 . The system of  claim 11 , wherein the map logic includes a map processor and map tables.  
     
     
         14 . The system of  claim 11 , wherein the segment identifier includes a source identifier and a segment identifier.  
     
     
         15 . The system of  claim 14 , wherein the segment identifier includes priority level indicator that is chosen from selected priority levels.  
     
     
         16 . The system of  claim 15 , wherein the one or more memory regions are associated with the source processors and the selected priority levels, and wherein the total number of memory regions is equal to the number of source processors times the number of selected priority levels.