Pseudo-NMOS logic having a feedback controller

Abstract

A pseudo-NMOS circuit includes a load PFET electrically connected between a power supply and an output node, and an NFET circuit having a plurality of inputs connected between the output node and ground. A feedback PFET is electrically connected between the power supply and the output node, in parallel with the load PFET, and is controlled by a signal at the output node of the pseudo-NMOS circuit.

What is claimed is:  
     
         1 . A pseudo-NMOS circuit comprising: 
 a first PFET electrically connected between a power supply and an output node;    an NFET circuit connected between said output node and ground and having a plurality of inputs; and,    a second PFET electrically connected between said power supply and said output node, said second PFET being controlled by a signal at said output node.    
     
     
         2 . The circuit as defined in  claim 1  further including a control circuit for turning said second PFET ON and OFF based on said signal at said output node.  
     
     
         3 . The circuit as defined in  claim 2  wherein said control circuit is electrically connected between said power supply and said ground, and has an input connected to said output node.  
     
     
         4 . The circuit as defined in  claim 3  wherein said control circuit is an inverter circuit including a PFET connected in series to an NFET, and wherein said PFET is electrically connected to said power supply, said NFET is connected to said ground, and gates of said PFET and NFET are connected to said output node.  
     
     
         5 . The circuit as defined in  claim 4  wherein a gate to said second PFET is connected to a feedback node connecting a drain of said PFET and a drain of said NFET of said inverter circuit.  
     
     
         6 . The circuit as defined in  claim 5  wherein a signal at said feedback node transitions LOW to turn ON said second PFET when said signal at said output node is HIGH, and said signal at said feedback node transitions HIGH to turn OFF said second PFET when said signal at said output node is LOW.  
     
     
         7 . The circuit as defined in  claim 1  wherein a gate of said first PFET is connected to said ground, and a gate of said second PFET is connected to a feedback signal from said output node.  
     
     
         8 . The circuit as defined in  claim 7  wherein said second PFET is turned ON when a signal at said output node is HIGH, and turned OFF when said signal at said output node is LOW.  
     
     
         9 . A pseudo-NMOS circuit for reducing output noise, said circuit comprising: 
 a load PFET electrically connected between a power supply and an output node;    an NFET circuit having a plurality of inputs connected between said output node and ground for performing a predetermined function based on signals applied to said inputs and outputting a signal to said output node; and,    a feedback PFET electrically connected between said power supply and said output node for reducing noise at said output node based on said signal at said output node.    
     
     
         10 . The circuit as defined in  claim 9  further including a feedback circuit electrically connected to said feedback PFET, wherein said feedback circuit sets said feedback PFET to ON when said signal at said output node is HIGH, and sets said feedback PFET to OFF when said signal at said output node is LOW.  
     
     
         11 . The circuit as defined in  claim 10  wherein an output of said feedback circuit is LOW when said signal at said output node is HIGH, and said output of said feedback circuit is HIGH when said signal at said output node is LOW.  
     
     
         12 . A method for reducing noise at an output of a pseudo-NMOS circuit having a load PFET and an NFET function circuit, said method comprising the steps of: 
 providing a second PFET in parallel with the load PFET between a power source and the NFET function circuit; and,    turning said second PFET ON when said output of the pseudo-NMOS circuit is HIGH, and turned OFF said second PFET when said output of the pseudo-NMOS circuit is LOW.    
     
     
         13 . The method as defined in  claim 12 , wherein said second PFET is turned ON and OFF by a feedback circuit connected to an output node of the pseudo-NMOS circuit.  
     
     
         14 . The method as defined in  claim 13 , wherein said feedback circuit is an inverter circuit having an input connected to said output of the pseudo-NMOS circuit and an output connected to said second PFET.