Semiconductor device

Abstract

A memory includes first circuit RFPDRAM including memory cells and operating in response to first clock signal, second circuit and third circuit coupled with first circuit and bus coupling first circuit to second and third circuits. The second circuit outputs in response to second clock signal, first address signal to first circuit. The third circuit outputs in response to third clock signal, second address signal to first circuit. The first circuit includes refresh control circuit executing refresh operation for memory cells in response to fourth clock signal and address latch for storing first or second address signal in response to first clock signal. The first clock signal has frequency equal to or more than sum of frequencies respectively of second, third, and fourth clock signals.

What is claimed is:  
     
         1 . A semiconductor device, comprising: 
 a first circuit including a plurality of memory cells, said first circuit operating in response to a first clock signal;    a second circuit and a third circuit which are coupled with said first circuit; and    a bus for coupling said first circuit to said second and third circuits, wherein:    said second circuit outputs, in response to a second clock signal, a first address signal to said first circuit;    said third circuit outputs, in response to a third clock signal, a second address signal to said first circuit;    said first circuit includes a refresh control circuit for executing a refresh operation for the memory cells in response to a fourth clock signal and an address latch for storing said first or second address signal in response to said first clock signal; and    said first clock signal has a frequency equal to or more than a sum of frequencies respectively of said second, third, and fourth clock signals.    
     
     
         2 . A semiconductor device according to  claim 1 , wherein when said frequency of said first clock signal is f, said frequencies fn respectively of said second, third, and fourth clock signals are represented as fn=f/2 j .  
     
     
         3 . A semiconductor device according to  claim 2 , further comprising a bus controller connected to said bus, said bus controller controlling said bus in response to said first clock signal.  
     
     
         4 . A semiconductor device according to  claim 1 , wherein said first circuit sequentially executes an operation to acquire said first and second address signals and said refresh operation in response to said first clock signal.  
     
     
         5 . A semiconductor device according to  claim 1 , wherein said first circuit comprises: 
 a first write bit line and a second write bit line;    a first read bit line and a second read bit line;    a first memory cell comprising 
 a first transistor and a second transistor which are connected in series between said first read bit line and a first potential and  
 a third transistor including a source-drain path connected between a gate of said second transistor and said first write bit line;  
   a second memory cell comprising 
 a fourth transistor and a fifth transistor which are connected in series between said second read bit line and said first potential and  
 a sixth transistor including a source-drain path connected between a gate of said fifth transistor and said second write bit line;  
 a first write word line connected to a gate of said third transistor;  
 a second write word line connected to a gate of said sixth transistor;  
 a read word line connected to gate respectively of said first and fourth transistors;  
 a column decoder connected to said address latch; and  
 a row decoder connected to said address latch and said column decoder.  
   
     
     
         6 . A semiconductor device according to  claim 5 , wherein said row address decoder comprises: 
 a first decoder circuit connected to aid address latch; and    a row selector circuit connected to said first decoder circuit and said column address decoder.    
     
     
         7 . A semiconductor device according to  claim 5 , wherein said first circuit comprises: 
 a write column selector connected to said column decoder for selecting said first or second write bit line; and    a read column selector connected to said column decoder for selecting said first or second read bit line; and    a latch circuit connected to said read column selector and said write column selector and said refresh operation is executed by inputting a data signal read from said first or second memory to said latch circuit via said read column selector, and by re-writing the data signal from said latch circuit via said write column selector to associated one of said first and second memory cells.    
     
     
         8 . A semiconductor device according to  claim 5 , wherein said first circuit further comprises: 
 a first latch circuit disposed on said first write bit line and said first read bit line; and    a second latch circuit disposed on said second write bit line and said second read bit line and said refresh operation is executed by selecting said first and second read word lines, and by re-writing the data via associated one of said first and second latch circuit.    
     
     
         9 . A semiconductor device according to  claim 1 , wherein said first circuit comprises: 
 a first write bit line and a second write bit line;    a first read bit line and a second read bit line;    a first memory cell comprising 
 a first transistor and a second transistor which are connected in series between said first read bit line and a first potential and  
 a third transistor including a source-drain path connected between a gate of said second transistor and said first write bit line;  
   a second memory cell comprising 
 a fourth transistor and a fifth transistor which are connected in series between said second read bit line and said first potential and  
 a sixth transistor including a source-drain path connected between a gate of said fifth transistor and said second write bit line;  
 a first word line connected to gate respectively of said first and third transistors;  
 a second word line connected to gate respectively of said fourth and sixth transistors;  
 a column decoder connected to said address latch; and  
 a row decoder connected to said address latch and said column decoder.  
   
     
     
         10 . A semiconductor device according to  claim 9 , wherein said row address decoder comprises: 
 a first decoder circuit connected to said address latch; and    a row selector circuit connected to said first decoder circuit and said column address decoder.    
     
     
         11 . A semiconductor device according to  claim 9 , wherein said first circuit comprises: 
 a write column selector connected to said column decoder for selecting said first or second write bit line; and    a read column selector connected to said column decoder for selecting said first or second read bit line; and    a latch circuit connected to said read column selector and said write column selector and    said refresh operation is executed by inputting a data signal read from said first or second memory to said latch circuit via said read column selector, and by re-writing the data signal from said latch circuit via said write column selector to associated one of said first and second memory cells.    
     
     
         12 . A semiconductor device according to  claim 9 , wherein said first circuit further comprises: 
 a first latch circuit disposed on said first write bit line and said first read bit line; and    a second latch circuit disposed on said second write bit line and said second read bit line, and    said refresh operation is executed by concurrently selecting said first and second read word lines, and by re-writing the data via associated one of said first and second latch circuit.    
     
     
         13 . A semiconductor device according to  claim 1 , wherein said refresh control circuit comprises a clock generator circuit for receiving said first clock signal and said second clock signal and for generating said fourth clock signal.  
     
     
         14 . A semiconductor device formed on a semiconductor substrate comprising: 
 a plurality of DRAM memory cells each having first, second, and third transistors and formed in a memory array;    a plurality of first word lines coupled to the gates of said first transistors;    a plurality of second word lines coupled to the gates of said second transistors;    a plurality of first bit lines coupled to the source/drain paths of said first transistors;    a plurality of second bit lines coupled to the source/drain paths of said second transistors;    a terminal fed with a clock signal from outside of said semiconductor device; and    an X address latch and a Y address latch, wherein each gate of said third transistor is coupled to the source/drain path of said first transistor, and each source/drain path of said third transistor is coupled to the source/drain path of said second transistor; and    means for eliminating rewrite operations to non-selected DRAM memory cells coupled to a selected word line, wherein read operation and write operation are pipelined where an operational cycle is related to row access.    
     
     
         15 . The semiconductor device according to  claim 14 , further comprising: 
 means for deferring conflicts in the timing of refreshing operations against said plurality of DRAM memory cells and access from outside of said semiconductor device.    
     
     
         16 . The semiconductor device according to  claim 15 , wherein said means for deferring conflicts comprises a circuit issuing the timing of said refreshing operations based on a clock cycle having a higher frequency than said clock signal.  
     
     
         17 . The semiconductor device according to  claim 15 , further comprising: 
 a selecting circuit to select one of said plurality of said first word lines,    wherein the number of said plurality of said first word lines is larger than the number of said plurality of said second word lines, and    wherein said selecting circuit is placed on one side of said memory array.    
     
     
         18 . The semiconductor device according to  claim 17 , 
 wherein the number of data inputted for writing data when one of said plurality of first word lines is selected is the number of said DRAM memory cells provided to said one of said plurality of first word lines, and    wherein said first word lines extend as long as said second word lines.    
     
     
         19 . The semiconductor device according to  claim 16 , further comprising: 
 a word driver circuit coupled to said plurality of said first word lines, and    wherein said word driver circuit is placed on one side of said memory array.