Semiconductor integrated circuit

Abstract

A semiconductor integrated circuit in which multiphase clock signals having the same phase difference are supplied from a multi-stage differential ring oscillator to other circuits, the multiphase clock signals can be prevented from being degraded in waveform due to electrostatic coupling between wirings of the multiphase clock signals and also wired in as small an area as possible. The semiconductor integrated circuit includes: multiple stages of amplifier circuits, connected in a ring form, for performing oscillating operation; a logic circuit for performing logic operation on the basis of predetermined ones of output signals of the multiple stages of amplifier circuits to output a plurality of clock signals having different phases from each other and duties not equal to 0.5; and a plurality of wirings for transmitting the plurality of clock signals output from the logic circuit.

1 . A semiconductor integrated circuit comprising: 
 multiple stages of amplifier circuits, connected in a ring form, for performing oscillating operation;    a logic circuit for performing logic operation on the basis of predetermined ones of output signals of said multiple stages of amplifier circuits to output a plurality of clock signals having different phases from each other and duties not equal to 0.5; and    a plurality of wirings for transmitting said plurality of clock signals output from said logic circuit.    
     
     
         2 . A semiconductor integrated circuit according to  claim 1 , further comprising a parallel-serial conversion circuit for converting input parallel data into serial data on the basis of said plurality of clock signals.  
     
     
         3 . A semiconductor integrated circuit according to  claim 1 , wherein each of said multiple stages of amplifier circuits amplifies a difference between a signal applied to a non-inverted input terminal and a signal applied to an inverted input terminal and supplies a differential signal thus obtained to a non-inverted output terminal and an inverted output terminal.  
     
     
         4 . A semiconductor integrated circuit according to  claim 1 , wherein a delay time of each of said multiple stages of amplifier circuits is controlled by one of a control voltage and a control current.  
     
     
         5 . A semiconductor integrated circuit according to  claim 1 , wherein said multiple stages of amplifier circuits include N stages of differential circuits and said logic circuit outputs M clock signals having different phases from each other, where N is a positive even number and M is an even number within a range from 2 to N.  
     
     
         6 . A semiconductor integrated circuit according to  claim 5 , wherein said logic circuit includes M AND gates, each obtaining logical multiply of two of the output signals of said multiple stages of amplifier circuits to output one clock signal.  
     
     
         7 . A semiconductor integrated circuit according to  claim 1 , wherein a first wiring and a second wiring are arranged parallel to each other and said first wiring undergoes voltage transition between a first voltage and a second voltage when said second wiring has the second voltage.  
     
     
         8 . A semiconductor integrated circuit according to  claim 7 , wherein said second voltage is a ground voltage.  
     
     
         9 . A semiconductor integrated circuit according to  claim 1 , wherein: 
 a first wiring and at least one wiring together form a set of wirings and said first wiring undergoes voltage transition between a first voltage and a second voltage when said at least one wiring has the second voltage; and    a distance between a wiring included in said set and a wiring not included in said set is larger than a distance between two adjacent wirings included in said set.    
     
     
         10 . A semiconductor integrated circuit according to  claim 9 , wherein said second voltage is a ground voltage.  
     
     
         11 . A semiconductor integrated circuit according to  claim 9 , wherein another wiring is arranged between said wiring included in said set and said wiring not included in said set.  
     
     
         12 . A semiconductor integrated circuit according to  claim 10 , wherein said another wiring is grounded.  
     
     
         13 . A semiconductor integrated circuit according to  claim 1 , wherein said multiple stages of amplifier circuits include N stages of differential circuits and said logic circuit outputs M clock signals having different phases from each other and duties not larger than (0.5−2/N), where N is a positive even number and M is an even number within a range from 2 to N.  
     
     
         14 . A semiconductor integrated circuit according to  claim 13 , wherein said logic circuit includes M AND gates, each obtaining logical multiply of two of the output signals of said multiple stages of amplifier circuits to output one clock signal.  
     
     
         15 . A semiconductor integrated circuit according to  claim 13 , wherein a first wiring and a second wiring are arranged parallel to each other and said first wiring undergoes voltage transition between a first voltage and a second voltage when said second wiring has the second voltage.  
     
     
         16 . A semiconductor integrated circuit according to  claim 15 , wherein said second voltage is a ground voltage.  
     
     
         17 . A semiconductor integrated circuit according to  claim 13 , wherein: 
 a first wiring and at least one wiring together form a set of wirings and said first wiring undergoes voltage transition between a first voltage and a second voltage when said at least one wiring has the second voltage; and    a distance between a wiring included in said set and a wiring not included in said set is larger than a distance between two adjacent wirings included in said set.    
     
     
         18 . A semiconductor integrated circuit according to  claim 17 , wherein said second voltage is a ground voltage.  
     
     
         19 . A semiconductor integrated circuit according to  claim 17 , wherein another wiring is arranged between said wiring included in said set and said wiring not included in said set.  
     
     
         20 . A semiconductor integrated circuit according to  claim 19 , wherein said another wiring is grounded.