Interposers for chip-scale packages, chip-scale packages including the interposers, test apparatus for effecting wafer-level testing of the chip-scale packages, and methods

Abstract

A carrier substrate, or interposer, for use in a chip-scale package. The interposer is formed from a material, such as a semiconductive material, that has a coefficient of thermal expansion that is the same or similar to that of the semiconductor device to be secured thereto. A chip-scale package including the interposer is formed by aligning a substrate including a plurality of interposers over semiconductor devices carried upon a wafer or other large-scale substrate. Bond pads of the semiconductor devices are exposed through insulator-lined apertures of the interposers. The apertures are filled with electrically conductive material and conductive structures are secured to the apertures so as to communicate with corresponding bond pads. The resulting chip-scale packages may then be severed or diced from the substrate and wafer. Apparatus and methods for simultaneously testing multiple, physically connected chip-scale packages are also disclosed.

What is claimed is:  
     
         1 . An interposer for use in a chip-scale package having at least one semiconductor device, said interposer comprising: 
 a substrate having a coefficient of thermal expansion substantially the same as a coefficient of thermal expansion of a semiconductor device of the chip-scale package, said substrate including a plurality of apertures formed therethrough at locations corresponding to locations of bond pads of said semiconductor device, each aperture having a length;    an electrically insulative lining covering at least one surface of each aperture of said plurality of apertures; and    conductive material at least partially filling each aperture and extending substantially along said length of each aperture.    
     
     
         2 . The interposer of  claim 1 , wherein said substrate comprises silicon.  
     
     
         3 . The interposer of  claim 1 , including a hollow region within said conductive material at least partially filling each aperture formed through said substrate.  
     
     
         4 . The interposer of  claim 1 , further comprising a plurality of contacts, each contact of said plurality of contacts positioned over an aperture of said plurality of apertures communicating with said conductive material in said aperture.  
     
     
         5 . The interposer of  claim 1 , wherein said substrate comprises a portion of a large-scale substrate for forming a plurality of interposers.  
     
     
         6 . The interposer of  claim 5 , wherein said large-scale substrate comprises a wafer of semiconductor material.  
     
     
         7 . A semiconductor device assembly, comprising: 
 a first large-scale substrate comprising a plurality of semiconductor devices formed thereon, each semiconductor device of said plurality of semiconductor devices including at least one bond pad on an active surface thereof;    a second large-scale substrate positioned adjacent said first large-scale substrate and including a plurality of interposers, each interposer of said plurality of interposers corresponding to a semiconductor device of said plurality of semiconductor devices and including at least one aperture formed therethrough, said at least one aperture aligned over said at least one bond pad of said corresponding semiconductor device; and    conductive material located within at least a portion of said at least one aperture, said conductive material extending substantially along a length of said at least one aperture and being bonded to said at least one bond pad.    
     
     
         8 . The semiconductor device assembly of  claim 7 , wherein said first large-scale substrate comprises a wafer of semiconductor material.  
     
     
         9 . The semiconductor device assembly of  claim 7 , wherein said second large-scale substrate comprises a wafer of semiconductor material.  
     
     
         10 . The semiconductor device assembly of  claim 7 , wherein said second large-scale substrate includes thin regions between adjacent interposers of said plurality of interposers.  
     
     
         11 . The semiconductor device assembly of  claim 10 , wherein said thin regions extend substantially through said second large-scale substrate.  
     
     
         12 . The semiconductor device assembly of  claim 7 , wherein each interposer includes at least one contact pad positioned over said at least one aperture in communication with said conductive material within at least said portion of said at least one aperture.  
     
     
         13 . The semiconductor device assembly of  claim 7 , further comprising an electrically insulative material disposed between said first large-scale substrate and said second large-scale substrate.  
     
     
         14 . The semiconductor device assembly of  claim 7 , including a hollow area within said conductive material within said at least one aperture of each interposer.  
     
     
         15 . The semiconductor device assembly of  claim 7 , further comprising at least one conductive structure protruding from each interposer on an opposite side thereof from said corresponding semiconductor device and communicating with said at least one bond pad of said corresponding semiconductor device.  
     
     
         16 . The semiconductor device assembly of  claim 7 , wherein at least some interposers of said plurality of interposers include laterally extending conductive traces communicating with said conductive material in at least said portion of said at least one aperture thereof.  
     
     
         17 . The semiconductor device assembly of  claim 7 , further comprising an additional interposer layer positioned adjacent each interposer of said plurality of interposers, opposite each interposer from said corresponding semiconductor device, said additional interposer layer including a laterally extending conductive trace and at least one contact pad, said at least one contact pad having a different lateral position relative to a plane of said corresponding semiconductor device than said at least one bond pad of said corresponding semiconductor device.  
     
     
         18 . The semiconductor device assembly of  claim 17 , wherein said additional interposer layer comprises a material having substantially the same coefficient of thermal expansion as a material of said first and second large-scale substrates.  
     
     
         19 . The semiconductor device assembly of  claim 18 , wherein said additional interposer layer comprises a semiconductor material.  
     
     
         20 . The semiconductor device assembly of  claim 17 , wherein said additional interposer layer comprises polyimide.  
     
     
         21 . A method for assembling a chip-scale package, comprising: 
 providing a semiconductor device having an active surface and having at least one bond pad on said active surface;    positioning an interposer over said active surface;    introducing conductive material into at least one aperture formed through said interposer and aligned over said at least one bond pad; and    bonding said conductive material to said at least one bond pad.    
     
     
         22 . The method of  claim 21 , wherein said providing said semiconductor device comprises providing at least one semiconductor die.  
     
     
         23 . The method of  claim 21 , wherein said providing said semiconductor device comprises providing a large-scale substrate having a plurality of semiconductor devices formed thereon.  
     
     
         24 . The method of  claim 23 , wherein said providing said large-scale substrate comprises providing a wafer including semiconductive material.  
     
     
         25 . The method of  claim 21 , wherein said positioning said interposer comprises positioning an interposer including semiconductive material over said semiconductor device.  
     
     
         26 . The method of  claim 21 , wherein said positioning said interposer comprises positioning a large-scale substrate including a plurality of interposers adjacent said semiconductor device.  
     
     
         27 . The method of  claim 26 , wherein said positioning said large-scale substrate comprises positioning a wafer including semiconductive material adjacent said semiconductor device.  
     
     
         28 . The method of  claim 21 , wherein said positioning said interposer comprises positioning an interposer having said at least one aperture formed therethrough.  
     
     
         29 . The method of  claim 21 , further comprising forming an aperture through said interposer substantially corresponding to said at least one bond pad on said active surface.  
     
     
         30 . The method of  claim 29 , wherein said an aperture occurs after said positioning of said interposer.  
     
     
         31 . The method of  claim 21 , further comprising forming a contact pad on said interposer adjacent said at least one aperture and in contact with said conductive material therein.  
     
     
         32 . The method of  claim 21 , further comprising positioning at least one conductive structure adjacent a surface of said interposer opposite said semiconductor device and communicating with said at least one bond pad.  
     
     
         33 . The method of  claim 21 , further comprising positioning another interposer over said interposer, opposite said semiconductor device, said another interposer including at least one laterally extending conductive element having a first end thereof alignable over said at least one bond pad and having a second end thereof located over another position of said semiconductor device other than said at least one bond pad.  
     
     
         34 . The method of  claim 33 , wherein said positioning another interposer comprises forming at least portions of said another interposer on said interposer.  
     
     
         35 . The method of  claim 33 , wherein said positioning another interposer comprises positioning a preformed interposer over said interposer.  
     
     
         36 . The method of  claim 33 , further comprising securing said another interposer to said interposer, said at least one conductive trace of said another interposer communicating with said at least one bond pad of said semiconductor device.  
     
     
         37 . The method of  claim 33 , further comprising positioning at least one conductive structure in communication with said second end of said at least one conductive element.  
     
     
         38 . A method for packaging semiconductor devices connected to one another on a large-scale substrate, comprising: 
 evaluating electrical properties of semiconductor devices on said large-scale substrate, each semiconductor device having contact pads;    identifying each semiconductor device on said large-scale substrate with desired electrical properties; and    securing conductive structures to said contact pads of each semiconductor device having said desired electrical properties.    
     
     
         39 . The method of  claim 38 , wherein said evaluating includes burn-in testing said semiconductor devices on said large-scale substrate.  
     
     
         40 . The method of  claim 38 , wherein said identifying includes mapping a position on said large-scale substrate of each semiconductor device having said desired electrical properties.  
     
     
         41 . The method of  claim 38 , wherein said evaluating said semiconductor devices includes evaluating a plurality of chip-scale packages.  
     
     
         42 . The method of  claim 41 , wherein said evaluating said plurality of chip-scale packages includes evaluating said plurality of chip-scale packages on a wafer scale.  
     
     
         43 . The method of  claim 38 , wherein said securing conductive structures includes securing at least one of balls, bumps, and pillars to said contact pads.  
     
     
         44 . The method of  claim 38 , wherein said securing conductive structures includes securing conductive structures including one of metal and a z-axis conductive elastomer to said contact pads.  
     
     
         45 . A method for fabricating a chip-scale package, comprising: 
 providing a first large-scale substrate including a plurality of semiconductor devices;    positioning a second large-scale substrate including a plurality of interposers over said first large-scale substrate, each interposer of said plurality of interposers substantially aligned adjacent a semiconductor device of said plurality of semiconductor devices;    securing said first and second large-scale substrates to one another; and    reducing a thickness of said second large-scale substrate at locations between adjacent interposers thereof.    
     
     
         46 . The method of  claim 45 , wherein said providing said first large-scale substrate comprises providing a wafer including a semiconductive material.  
     
     
         47 . The method of  claim 46 , wherein said providing said wafer comprises providing a silicon wafer.  
     
     
         48 . The method of  claim 45 , wherein said providing said second large-scale substrate comprises providing a wafer including a semiconductive material.  
     
     
         49 . The method of  claim 48 , wherein said providing said wafer comprising providing a silicon wafer having surfaces thereof at least partially aligned with an electrically insulative material.  
     
     
         50 . The method of  claim 45 , wherein said positioning comprises aligning bond pads of each semiconductor device of said plurality of semiconductor devices and apertures of a corresponding interposer of said plurality of interposers.  
     
     
         51 . The method of  claim 45 , wherein said securing comprises: 
 introducing conductive material into apertures formed through said second large-scale substrate; and    bonding said conductive material to bond pads that correspond to said apertures.    
     
     
         52 . The method of  claim 45 , wherein said reducing said thickness comprises reducing said thickness at locations of said second large-scale substrate overlying streets located between adjacent semiconductor devices of said plurality of semiconductor devices.  
     
     
         53 . The method of  claim 46 , wherein said reducing said thickness comprises etching said second large-scale substrate at said locations.  
     
     
         54 . The method of  claim 45 , wherein said reducing said thickness comprises exposing said locations of said second large-scale substrate to an energy beam.  
     
     
         55 . The method of  claim 54 , wherein said exposing comprises exposing said locations to a laser beam.  
     
     
         56 . The method of  claim 45 , wherein said reducing said thickness comprises substantially removing material of said second large-scale substrate at each of said locations.  
     
     
         57 . The method of  claim 46 , further comprising severing said first and second large-scale substrates at each of said locations.  
     
     
         58 . A wafer-scale testing system comprising: 
 a substrate receptacle; and    a test chuck configured to be positioned within said substrate receptacle, said test chuck including a plurality of terminals, each terminal of said plurality for contacting conductive structures protruding from at least one semiconductor device on a large-scale substrate, each terminal of said plurality of terminals for communicating with a test apparatus upon positioning said test chuck within said substrate receptacle, said test chuck formed from a material having substantially the same coefficient of thermal expansion as a material of said large-scale substrate.    
     
     
         59 . The system of  claim 58 , wherein each terminal of said plurality of terminals is configured to at least partially receive one of said conductive structures.  
     
     
         60 . The system of  claim 58 , wherein said test chuck comprises silicon.  
     
     
         61 . The system of  claim 58 , wherein said test chuck is used for testing a plurality of physically connected chip-scale packages, each chip-scale package of said plurality including at least one semiconductor die and an interposer, said interposer comprising a material having substantially the same coefficient of thermal expansion as a material of said at least one semiconductor die.  
     
     
         62 . The system of  claim 61 , wherein said test chuck is used for testing a chip-scale package including a semiconductor die comprising silicon and an interposer comprising silicon.  
     
     
         63 . The system of  claim 58 , wherein said test chuck includes a plurality of apertures therethrough, each aperture of said plurality of apertures positioned for communicating between a terminal of said plurality of terminals and a test probe insertable into said each aperture.  
     
     
         64 . The system of  claim 63 , wherein each aperture of said test chuck is lined with an electrically insulative material.  
     
     
         65 . The system of  claim 58 , further comprising a lid disposable over said substrate receptacle so as to bias said at least one semiconductor device therein against said test chuck positioned therein.