Using non-volatile memories for disk caching

Abstract

A disk cache may include a volatile memory such as a dynamic random access memory and a nonvolatile memory such as a polymer memory. When a cache line needs to be allocated on a write, the polymer memory may be allocated and when a cache line needs to be allocated on a read, the volatile memory may be allocated.

What is claimed is:  
     
         1 . A method comprising: 
 determining whether a cache line needs to be allocated on a read and, if so, allocating the cache line to a volatile memory disk cache; and    determining if a cache line needs to be allocated on a write and, if so, allocating the write to a polymer memory disk cache.    
     
     
         2 . The method of  claim 1  including allocating a cache line read to a dynamic random access memory.  
     
     
         3 . The method of  claim 1  including, after a predetermined time, transferring data from the polymer or memory disk cache to the volatile memory disk cache.  
     
     
         4 . The method of  claim 1  including transferring data written to a cache line in the volatile memory cache to the polymer memory cache.  
     
     
         5 . The method of  claim 1  including moving a cache line read from the polymer memory cache to the volatile memory cache.  
     
     
         6 . A disk cache comprising: 
 a polymer memory; and    a volatile memory.    
     
     
         7 . The cache of  claim 6  wherein said polymer memory and said volatile memory are coupled to exchange data.  
     
     
         8 . The cache of  claim 6  wherein said volatile memory is a dynamic random access memory.  
     
     
         9 . The cache of  claim 6  wherein a cache line read is allocated to the volatile memory cache.  
     
     
         10 . The cache of  claim 6  wherein a cache line write is allocated to the polymer memory cache.  
     
     
         11 . The cache of  claim 6  wherein, after a period of time, data written in the polymer memory is automatically moved to the volatile memory cache.  
     
     
         12 . The disk cache of  claim 6 , wherein the polymer memory is a destructive read memory device.  
     
     
         13 . A processor-based system comprising: 
 a processor;    a disk cache coupled to said processor, said disk cache including a volatile memory disk cache and a polymer memory disk cache; and    a wireless interface coupled to said processor.    
     
     
         14 . The system of  claim 13  wherein said volatile memory disk cache is a dynamic random access memory.  
     
     
         15 . The system of  claim 13  including a disk drive coupled to said cache and to said processor.  
     
     
         16 . The system of  claim 13  wherein said volatile memory cache is coupled to said polymer memory cache.  
     
     
         17 . The system of  claim 13  wherein data written to said polymer memory cache is automatically transferred to said volatile memory cache after a period of time.  
     
     
         18 . An article comprising a medium storing instruction that, if executed, enable a processor-based system to: 
 determine whether a cache line needs to be allocated on a read and, if so, allocate the cache line to a volatile memory disk cache; and    determine if a cache line needs to be allocated on a write and, if so, allocate the write to a polymer memory disk cache.    
     
     
         19 . The article of  claim 18  further storing instructions that, if executed, enable a processor-based system to move data written in the polymer memory disk cache to said volatile memory cache after the data has been stored on the polymer memory disk cache for a predetermined time period.  
     
     
         20 . A method comprising: 
 saving a partition table entry from a disk to a disk cache; and    scrambling the entry on the disk.    
     
     
         21 . The method of  claim 20  including redirecting an access to said entry on said disk to said cache.  
     
     
         22 . The method of  claim 20  including restoring said entry to the disk from the cache.  
     
     
         23 . The method of  claim 22  including determining whether disk caching is enabled and, if so, restoring said entry to the disk.  
     
     
         24 . An article comprising a medium storing instructions that, if executed, enable a processor-based system to: 
 save a partition table entry from a disk to a disk cache; and    scramble the entry on the disk.    
     
     
         25 . The article of  claim 24  further storing instructions to redirect an access to said entry on said disk to said disk cache.  
     
     
         26 . The article of  claim 24  further storing instructions to restore said entry to the disk from the cache.  
     
     
         27 . The article of  claim 26  further storing instructions to determine whether disk caching is disabled and, if so, to restore said entry to said disk.  
     
     
         28 . A system comprising: 
 a processor;    a disk cache coupled to said processor;    a storage coupled to said processor storing instructions that, if executed, enable a processor-based system to save a partition table entry from a disk to the disk cache and scramble the entry on the disk; and    a wireless interface.    
     
     
         29 . The system of  claim 28  including a disk drive.  
     
     
         30 . The system of  claim 28  wherein said cache includes a polymer memory.  
     
     
         31 . The system of  claim 28  wherein said storage stores instructions to redirect an access to said entry on said disk to said disk cache.  
     
     
         32 . The system of  claim 28  wherein said storage stores instructions to restore said entry to the disk from the cache.  
     
     
         33 . The system of  claim 32  wherein said storage storing instructions to determine whether disk caching is enabled and, if so, to restore said entry to said disk.  
     
     
         34 . A disk cache comprising: 
 a ferroelectric memory; and    a volatile memory.    
     
     
         35 . The cache of  claim 34  wherein said ferroelectric memory and said volatile memory are coupled to exchange data.