Semiconductor device and mounted semiconductor device structure

Abstract

A small semiconductor device which can be fabricated at the wafer level has high reliability of external terminals with respect to distortion caused by differential thermal expansion between a semiconductor element of the device and a printed circuit board and has superior electrical performance achieved through reduced static capacitance of interconnections. A thick stress-moderating layer with a low elastic modulus is interposed between the semiconductor element and interconnections and lands and improves the reliability of external terminals by absorbing distortion caused by the differential thermal expansion. The thick stress-moderating layer also reduces static capacitance between the interconnections and internal interconnections of the semiconductor element. Even around element electrodes, where the stress-moderating layer is not formed, static capacitance is reduced by an insulating film interposed between the interconnections and the semiconductor element.

What is claimed is:  
     
         1 . A method of manufacturing semiconductor devices each having a semiconductor element, comprising: 
 forming a stress-moderating layer on a wafer on which the semiconductor devices element electrodes and an insulating layer with openings over said element electrodes are formed;    forming a land and an interconnection connecting said land to one of said element electrodes, wherein one part of said interconnection faces said insulating layer, and another part of the interconnection faces said stress-moderating layer; and    dicing said wafer having said land into said semiconductor devices.    
     
     
         2 . A method according to  claim 1 , wherein an passivation layer is formed between said semiconductor element and said insulating layer.  
     
     
         3 . A method according to  claim 1 , wherein the area of said insulating layer is smaller than the area of said wafer.  
     
     
         4 . A method according to  claim 1 , wherein the area of said stress-moderating layer is smaller than the area of said wafer.  
     
     
         5 . A method of manufacturing semiconductor devices each having a semiconductor element, comprising: 
 forming a stress-moderating layer on a wafer on which the semiconductor devices, element electrodes and an insulating layer with openings over said element electrodes are formed;    forming a land and an interconnection connecting said land to one of said element electrodes;    forming a surface protection film with openings over said element electrodes; and    dicing said wafer into said semiconductor devices,    wherein one part of said interconnection faces said insulating layer, and another part of said interconnection faces said stress-moderating layer.    
     
     
         6 . A method according to  claim 1 , wherein edges of said insulating layer and said surface protection film are located outside a dicing area on said wafer.