Semiconductor integrated circuit with memory redundancy circuit

Abstract

A semiconductor memory device comprising a redundancy circuit having a small area and high repair efficiency in which time required to store the address of a defect is short and which can reduce the manufacturing cost of the device is disclosed. Repairing addresses are sorted and stored in accordance with a specific order. In case of storing four addresses for eight addresses, a set SFG of fuses corresponding to eight decoded addresses DA 0 to DA 7 is provided and information indicative of the ordinal position of the fuse in the corresponding fuse-decision results which are logic 1 is used to associate the address with the repair-decision result.

What is claimed is:  
     
         1 . A semiconductor device comprising: 
 a plurality of memory circuits designated by ND (ND=2{circumflex over ( )}NA) addresses expressed by a binary address of NA bits; and    a defect address storing circuit including ND storage elements for storing NS (NS=two and over) defect addresses in relation to a plurality of defects in the plurality of memory circuits,    wherein the NS defect addresses are addresses which are different from each other selected from the ND addresses, and    each of the ND storage elements stores a first logical state or a second logical state in one bit.    
     
     
         2 . A semiconductor device according to  claim 1 , 
 wherein an initial value of each of the ND storage elements is in the first logical state and the NS storage elements in the ND storage elements are programmed into the second logical state, thereby storing the NS defect addresses.    
     
     
         3 . A semiconductor device according to  claim 1 , 
 wherein each of the NS defect addresses is expressed by a decoded address of ND bits,    wherein one bit of the decoded address of ND bits is in the second logical state and the other bits are in the first logical state, and    wherein the bits in the second logical state of the NS defect addresses are sequentially programmed into the ND storage elements in accordance with the order from the address having a smaller number to the address having a larger number.    
     
     
         4 . A semiconductor device according to  claim 1 , 
 wherein NS>(2{circumflex over ( )}NA)/(NA+1) is satisfied.    
     
     
         5 . A semiconductor device according to  claim 1 , 
 wherein each of the plurality of memory circuits includes a plurality of memory cells provided at intersecting points of a plurality of word lines and a plurality of bit lines and    wherein the number of the plurality of memory circuits is ND.    
     
     
         6 . A semiconductor device according to  claim 5 , further comprising: a flexible column redundancy circuit for repairing a defect in the bit lines in the plurality of memory circuits, 
 wherein the defect address storing circuit is included in the flexible column redundancy circuit, and    wherein the ND storage elements store addresses of the plurality of memory circuits relating to a defect.    
     
     
         7 . A semiconductor device according to  claim 1 , 
 wherein each of the ND storage elements is a fuse circuit for storing the first logical state as an initial value and storing the second logical state by being programmed.    
     
     
         8 . A semiconductor device comprising: 
 a plurality of memory circuits designated by ND (ND=2{circumflex over ( )}NA) addresses expressed by binary addresses of NA bits; and    a defect address storing circuit including (ND+NS−1) storage elements for storing NS (NS=two and over) defect addresses in relation to a plurality of defects in the plurality of memory circuits,    wherein the NS defect addresses can be selected in such a manner that the same address selected from the ND addresses may be repeated,    wherein each of the (ND+NS−1) storage elements stores a first logical state or a second logical state in one bit, and    wherein NS is larger than ND.    
     
     
         9 . A semiconductor device according to  claim 8 , 
 wherein the (ND+NS−1) storage elements are divided into a first group of ND storage elements as a first array and a second group of (NS−1) storage elements as a second array,    wherein the first group of ND storage elements store independent addresses which are different from each other in the ND addresses, and    wherein the second group of (NS−1) storage elements store the number of duplex selection of an address which is repeated in the independent addresses.    
     
     
         10 . A semiconductor device according to  claim 9 , 
 wherein each of the NS defect addresses is expressed by a decoded address of ND bits,    wherein one bit in the ND bits of the decoded address is in the second logical state and the other bits are in the first logic stage, and    wherein the bits in the second logical state of the NS defect addresses are sequentially programmed into the first group of ND storage elements in accordance with the order from the address having a smaller number to the address having a larger number.    
     
     
         11 . A semiconductor device according to  claim 8 , 
 wherein NS>((2{circumflex over ( )}NA)+1)/NA is satisfied.    
     
     
         12 . A semiconductor device according to  claim 8 , 
 wherein each of the plurality of memory circuits has a plurality of memory cells provided at intersecting points of a plurality of word lines and a plurality of bit lines, and    wherein the number of the plurality of memory circuits is ND.    
     
     
         13 . A semiconductor device according to  claim 12 , further comprising a flexible column redundancy circuit for repairing a plurality of defects, each defect is associated with a bit line in one of the plurality of memory circuits, 
 wherein the defect address storing circuit is included in the flexible column redundancy circuit, and    wherein the (ND+NS−1) storage elements store addresses of the plurality of memory circuits related to the plurality of defects.    
     
     
         14 . A semiconductor device according to  claim 13 , 
 wherein each of the (ND+NS−1) storage elements is a fuse circuit for storing the first logical state as an initial value and storing the second logical state by being programmed.    
     
     
         15 . A semiconductor device comprising: 
 a plurality of memory blocks each having a plurality of memory cells provided at intersecting points of a plurality of bit lines and a spare bit line which cross a plurality of word lines;    a plurality of column selection lines, each provided for one of the plurality of bit lines of the plurality of memory blocks;    a spare column selection line provided for the spare bit line of the plurality of memory blocks; and    a redundancy circuit having an input node to which an access address including a first access information for designating one of the plurality of memory blocks and a second access information for designating one of the plurality of column selection lines is supplied, a defect address storing circuit for storing a plurality of defect addresses, and an output node which is coupled to the spare column selection line to make the spare column selection line active when the access address coincides with the plurality of defect addresses,    wherein the defect address storing circuit further includes a first storage set for storing a first information to designate one of the plurality of column selection lines related to a first defect, a second storage set for storing a second information for designating one of the plurality of column selection lines related to a second defect, and a third storage set for storing a third information for designating one of the plurality of memory blocks related to the first defect and a fourth information for designating another one of the plurality of memory blocks related to the second defect, and    wherein the third storage set has a plurality of storage elements of the number equal to the number of the plurality of memory blocks, which are provided as an array and stores the third and fourth information by the plurality of storage elements.    
     
     
         16 . A semiconductor device according to  claim 15 , 
 wherein one of the plurality of memory blocks in which the first defect is included is designated by programming corresponding one of the plurality of storage elements,    wherein another one of the plurality of memory blocks in which the second defect is included is designated by programming another corresponding one of the plurality of storage elements,    wherein the storage element programmed first in the array of the plurality of storage elements is associated with the first storage set, and    wherein the storage element programmed second in the array of the plurality of storage elements is associated with the second storage set.    
     
     
         17 . A semiconductor device according to  claim 15 , 
 wherein the defect address storing circuit further includes a fourth storage set for storing information to select one or plural memory blocks which is/are neighboring one of the plurality of memory blocks selected by the third storage set in relation to the first defect.    
     
     
         18 . A semiconductor device according to  claim 17 , further comprising a plurality of sense amplifiers which are provided between one of the plurality of memory blocks and another neighboring one of the plurality of memory blocks and are commonly used by the plurality of bit lines in one of the plurality of memory blocks and another neighboring one of the plurality of memory blocks, and 
 wherein the first defect is a defect related to one of the plurality of sense amplifiers coupled to one of the plurality of bit lines related to one of the plurality of column selection lines.    
     
     
         19 . A semiconductor device according to  claim 15 , wherein the redundancy circuit further comprises a shifter having a plurality of first input nodes to which the first access information is inputted in a decoded address format, a plurality of first output nodes of the number smaller than the number of the plurality of first input nodes, and a switch circuit for setting a plurality of logical connecting paths between the plurality of first input nodes and the plurality of first output nodes, 
 wherein the plurality of logical connecting paths are determined by the information stored in the plurality of storage elements in the third storage set.    
     
     
         20 . A semiconductor device according to  claim 19 , 
 wherein one of the plurality of first output nodes determines whether the result of comparison between the first information stored in the first storage set and the first access information is made valid or not, and    wherein another one of the plurality of first output nodes determines whether the result of comparison between the second information stored in the second storage set and the first access information is made valid or not.    
     
     
         21 . A semiconductor device according to  claim 15 , 
 wherein the first storage set includes a plurality of first storage elements and stores the first information in a binary address format,    wherein the second storage set includes a plurality of second storage elements and stores the second information in a binary address format, and    wherein the plurality of storage elements in the third storage set store the third and fourth information in a decoded address format obtained by decoding the information in the binary address format.    
     
     
         22 . A semiconductor device according to  claim 15 , further comprising a plurality of address input terminals to which a row address and a column address are supplied by an address multiplexing method, 
 wherein the first access information is obtained from the row address and the second access information is obtained from the column address, and    wherein the semiconductor device is a dynamic random access memory.    
     
     
         23 . A semiconductor device according to  claim 15 , 
 wherein each of the plurality of storage elements is a fuse circuit which stores the first logical state as an initial value and stores the second logical state when being programmed.    
     
     
         24 . A semiconductor device comprising: 
 a plurality of memory blocks, each having a plurality of memory cells provided at intersecting points of a plurality of bit lines, a first spare bit line, and a second spare bit line which cross a plurality of word lines;    a plurality of column selection lines, each provided for one of the plurality of bit lines of the plurality of memory blocks;    a first spare column selection line provided for the first spare bit line of the plurality of memory blocks;    a second spare column selection line provided for the second spare bit line of the plurality of memory blocks; and    a redundancy circuit having a first input node to which an access address including a first access information for designating one of the plurality of memory blocks and a second access information for designating one of the plurality of column selection lines is supplied, a defect address storing circuit for storing a plurality of defect addresses, a first output node which is coupled to the first spare column selection line to make the first spare column selection line active when the access address coincides with one of the plurality of defect addresses, and a second output node connected to the second spare column selection line to make the second spare selection line active when the access address coincides with another one of the plurality of defect addresses,    wherein the defect address storing circuit further includes: a first storage set which is provided to determine selection of the first spare column selection line, for storing a first information to designate one of the plurality of column selection lines related to a first defect; a second storage set which is provided to determine selection of the second spare column selection line, for storing a second information to designate one of the plurality of column selection lines related to a second defect; a third storage set for storing a third information for designating a first memory block as one of the plurality of memory blocks related to the first defect and a fourth information for designating a second memory block as one of the plurality of memory blocks related to the second defect,    wherein the third storage set has: a plurality of first storage elements for storing addresses of independent memory blocks which are different from each other in the first and second memory blocks; and a plurality of second storage elements for storing the number of duplex selection of addresses which are repeated in the independent memory blocks.    
     
     
         25 . A semiconductor device according to  claim 24 , 
 wherein the redundancy circuit further comprises: 
 a first shifter including a plurality of first input nodes to which the first access information is inputted in a decoded address format, a plurality of first output nodes of the same number as the number of the plurality of first input nodes, and a first switch circuit for setting a plurality of first logical connecting paths between the plurality of first input nodes and the plurality of first output nodes; and  
 a second shifter including a plurality of second input nodes connected to the plurality of first output nodes, a plurality of second output nodes of the number larger than the number of the plurality of second input nodes, and a second switch circuit for setting a plurality of second logical connecting paths between the plurality of second input nodes and the plurality of second output nodes,  
   wherein the plurality of first logical connecting paths are determined by information stored in the plurality of first storage elements in the third storage set, and    wherein the plurality of second logical connecting paths are determined by information stored in the plurality of second storage elements in the third storage set.    
     
     
         26 . A semiconductor device according to  claim 25 , 
 wherein an output of one of the plurality of second output nodes determines whether the result of comparison between the first information stored in the first storage set and the second access information is made valid or not, and    wherein an output of another one of the plurality of second output nodes determines whether the result of comparison between the second information stored in the second storage set and the second access information is made valid or not.    
     
     
         27 . A semiconductor device according to  claim 24 , 
 wherein the first storage set includes a plurality of third storage elements and stores the first information in a binary address format,    wherein the second storage set includes a plurality of fourth storage elements and stores the second information in a binary address format, and    wherein the plurality of first storage elements in the third storage set store the third and fourth information in a decoded address format obtained by decoding the information in the binary address format.    
     
     
         28 . A semiconductor device according to  claim 24 , further comprising a plurality of address input terminals to which a row address and a column address are supplied in an address multiplexing method, 
 wherein the first access information is obtained from the row address and the second access information is obtained from the column address, and    wherein the semiconductor device is a dynamic random access memory.    
     
     
         29 . A semiconductor device according to  claim 24 , 
 wherein each of the plurality of first and second storage elements is a fuse circuit which stores the first logical state as an initial value and stores the second logical state when being programmed.    
     
     
         30 . A semiconductor device comprising: 
 a first memory block having a plurality of first memory cells provided at intersecting points of a plurality of first bit lines which cross a plurality of first word lines and a first spare word line;    a second memory block having a plurality of second memory cells provided at intersecting points of a plurality of second bit lines which cross a plurality of second word lines and a second spare word line; and    a redundancy circuit having a first input node to which an access address including a first access information for designating one of the first and second memory blocks and a second access information for designating either one of the plurality of first word lines or one of the plurality of second word lines is supplied, a defect address storing circuit for storing a plurality of defect addresses, a first output node connected to the first spare word line in order to make the first spare word line active when the access address coincides with one of the plurality of defect addresses, and a second output node connected to the second spare word line to make the second spare word active when the access address coincides with another one of the plurality of defect addresses,    wherein the defect address storing circuit includes: 
 a first storage set provided to determine selection of the first spare word line, for storing a first information indicative of either one of the plurality of first word lines or one of the plurality of second word lines related to a first defect; a second storage set provided to determine selection of the second spare word line, for storing a second information indicative of either one of the plurality of first word lines or one of the plurality of second word lines related to a second defect; and a third storage set for storing a third information indicative one of the first and second memory blocks related to the first defect and fourth information indicative of the first or second memory block related to the second defect, and  
   wherein the third storage set has a plurality of first storage elements for storing addresses of independent memory blocks which are different from each other in the first and second memory blocks and a plurality of second storage elements for storing the number of duplex selection of addresses which are repeated in the addresses of the independent memory blocks.    
     
     
         31 . A semiconductor device according to  claim 30 , 
 wherein the redundancy circuit further comprises: 
 a first shifter including a plurality of first input nodes to which the first access information is inputted in a decoded address format, a plurality of first output nodes of the same number as the number of the plurality of first input nodes, and a first switch circuit for setting a plurality of first logical connecting paths between the plurality of first input nodes and the plurality of first output nodes; and  
 a second shifter including a plurality of second input nodes connected to the plurality of first output nodes, a plurality of second output nodes of the number larger than the number of the plurality of second input nodes, and a second switch circuit for setting a plurality of second logical connecting paths between the plurality of second input nodes and the plurality of second output nodes,  
   wherein the plurality of first logical connecting paths are determined by information stored in the plurality of first storage elements in the third storage set, and    wherein the plurality of second logical connecting paths are determined by information stored in the plurality of second storage elements in the third storage set.    
     
     
         32 . A semiconductor device according to  claim 31 , 
 wherein an output of one of the plurality of second output nodes determines whether the result of comparison between the first information stored in the first storage set and the second access information is made valid or not, and    wherein an output of another one of the plurality of second output nodes determines whether the result of comparison between the second information stored in the second storage set and the second access information is made valid or not.    
     
     
         33 . A semiconductor device according to  claim 30 , 
 wherein the first storage set includes a plurality of third storage elements and stores the first information in a binary address format,    wherein the second storage set includes a plurality of fourth storage elements and stores the second information in the binary address format, and    wherein the plurality of first storage elements in the third storage set store the third and fourth information in a decoded address format obtained by decoding the information in the binary address format.    
     
     
         34 . A semiconductor device according to  claim 30 , 
 wherein the first access information is obtained from higher bits of a row address and the second access information is obtained from lower bits of the row address, and    wherein the semiconductor device is a dynamic random access memory.    
     
     
         35 . A semiconductor device according to  claim 30 , 
 wherein each of the plurality of first and second storage elements is a fuse circuit which stores the first logical state as an initial value and stores the second logical state when being programmed.