Processor architecture

Abstract

There is described a processor architecture, comprising: a plurality of first bus pairs, each first bus pair including a respective first bus running in a first direction (for example, left to right) and a respective second bus running in a second direction opposite to the first direction (for example right to left); a plurality of second bus pairs,each second bus pair including a respective third bus running in a third direction (for example downwards) and a respective fourth bus running in a fourth direction opposite to the third direction (for example upwards), the third and fourth buses intersecting the first and second buses; a plurality of switch matrices, each switch matrix located at an intersection of a first and a second pair of buses; a plurality of elements arranged in an array, each element being arranged to receive data from a respective first or second bus, and transfer data to a respective first or second bus. The elements in the array include processing elements, for operating on received data, and memory elements, for storing received data. The described architecture has the advantage that it requires relatively little memory, and the memory requirements can be met by local memory elements in the array.

1 . A processor architecture, comprising: 
 a plurality of first bus pairs, each first bus pair including a respective first bus running in a first direction and a respective second bus running in a second direction opposite to the first direction;    a plurality of second bus pairs, each second bus pair including a respective third bus running in a third direction and a respective fourth bus running in a fourth direction opposite to the third direction, the third and fourth buses intersecting the first and second buses;    a plurality of switch matrices, each switch matrix located at an intersection of a first and a second pair of buses;    a plurality of elements arranged in an array, each element being arranged to receive data from a respective first or second bus, and transfer data to a respective first or second bus.    
     
     
         2 . A processor architecture as claimed in  claim 1 , wherein the elements in the array include processing elements, for operating on received data.  
     
     
         3 . A processor architecture as claimed in  claim 1 , wherein the elements in the array include memory elements, for storing received data.  
     
     
         4 . A processor architecture as claimed in  claim 1 , wherein the elements in the array include processing elements, for operating on received data, and memory elements, for storing received data.  
     
     
         5 . A processor architecture as claimed in  claim 2  or  4 , wherein the processing elements include Arithmetic Logic Units.  
     
     
         6 . A processor architecture as claimed in  claim 2 ,  4  or  5 , wherein the processing elements include Multiplier Accumulators.  
     
     
         7 . A processor architecture as claimed in any preceding claim, wherein the elements in the array further include interface elements for receiving input data from outside the processor, and transferring output data outside the processor.  
     
     
         8 . A processor architecture as claimed in any preceding claim, wherein each element of the array is connected between a first bus of one first bus pair and a second bus of an adjacent first bus pair.  
     
     
         9 . A processor architecture as claimed in any preceding claim, each element of the array having: 
 a first input for receiving data from the first bus of the one first bus pair;    a first output for transferring data to the first bus of the one first bus pair;    a second input for receiving data from a second bus of the adjacent first bus pair;    a second output for transferring data to the second bus of the adjacent first bus pair.    
     
     
         10 . A processor architecture as claimed in any preceding claim, further comprising: 
 a first switch connected to the first output of each element of the array, the first switch allowing either data on the first bus or data at the first output of the element of the array to pass along the first bus; and    a second switch connected to the second output of each element of the array, the second switch allowing either data on the second bus or data at the second output of the element of the array to pass along the second bus.    
     
     
         11 . A processor architecture as claimed in  claim 10 , wherein each first switch, connected to the first output of a respective element of the array, and each second switch, connected to the second output of the respective element of the array, are controlled by the respective element of the array.  
     
     
         12 . A processor architecture as claimed in any preceding claim, wherein each switch matrix allows data on a bus of a first bus pair to be switched onto the other bus of said first bus pair and/or onto either bus or both buses of the respective intersecting second bus pair, and allows data on a bus of a second bus pair to be switched onto either bus or both buses of the respective intersecting first bus pair, but not onto the other bus of said second bus pair.  
     
     
         13 . A processor architecture as claimed in  claim 12 , further comprising means for controlling each switch matrix.  
     
     
         14 . A processor architecture as claimed in  claim 11 , wherein the means for controlling each switch matrix comprises an array element.  
     
     
         15 . A processor architecture as claimed in any preceding claim, having a plurality of array elements connected to each bus of a first bus pair between each pair of adjacent switch matrices.  
     
     
         16 . A processor architecture as claimed in  claim 15 , having four array elements connected to each bus of a first bus pair between each pair of adjacent switch matrices.  
     
     
         17 . A processor architecture as claimed in any preceding claim, wherein each switch matrix comprises: 
 input and output connections for the respective first, second, third and fourth buses; and    four multiplexers, which are each controllable such that any one of their inputs can appear at their output, wherein 
 a first multiplexer ( 501 ) has inputs connected to input connections on first, second and third buses and an output connected to the third bus,  
 a second multiplexer ( 502 ) has inputs connected to input connections on first, second and fourth buses and an output connected to the fourth bus,  
 a third multiplexer ( 503 ) has inputs connected to input connections on first, second, third and fourth buses and an output connected to the first bus, and  
 a fourth multiplexer ( 504 ) has inputs connected to input connections on first, second, third and fourth buses and an output connected to the second bus.  
   
     
     
         18 . A processor architecture as claimed in  claim 17 , wherein the first, second, third and fourth multiplexers are 4:1 multiplexers, and the first and second multiplexers each have respective inputs which are held at zero.