US2004076166A1PendingUtilityA1

Multi-service packet network interface

Priority: Oct 21, 2002Filed: Jan 21, 2003Published: Apr 22, 2004
Est. expiryOct 21, 2022(expired)· nominal 20-yr term from priority
H04L 12/4604H04J 3/1611
44
PatentIndex Score
0
Cited by
0
References
0
Claims

Abstract

An integrated circuit device for use in providing packet service via multiple lower speed communications links and methods of operation of same is disclosed. The device may be capable of supporting Ethernet packet network service using a bonded group of time division multiplex or digital subscriber loop communications links by distributing the data traffic over the individual connections in the group. An embodiment of the invention may also include SONET/SDH compatible optical carrier framing, cross connect, and packet mapping functionality. It may include a telecom bus compatible interface for the connection of additional communications devices, and may incorporate an M13 multiplexer to permit the merging of multiple DS1 data streams into a single DS3 data stream. An embedded microprocessor core and embedded memory may permit an embodiment to support enhanced remote diagnostic, trouble reporting, traffic management, and software update capabilities.

Claims

exact text as granted — not AI-modified
What is claimed is:  
     
         1 . A data communications device comprising: 
 a hashing processor for selecting a transmit data channel and for designating a receive packet interface and a transmit packet interface;    a packet mapper for processing at least one transmit packet from the designated transmit packet interface operating at a first bit rate, the packet mapper transferring the contents of the at least one transmit packet to the selected transmit data channel, the packet mapper also for processing data from at least one receive data channel producing at least one receive packet for transmission on the designated receive packet interface operating at the first bit rate; and    at least one communication interface for serializing data from the transmit data channel to form a transmit data stream, and for passing to the receive data channel deserialized data from a receive data stream, the transmit data stream and receive data stream operating at a second bit rate.    
     
     
         2 . The data communications device of  claim 1  wherein the first bit rate is greater than the second bit rate.  
     
     
         3 . The data communication device of  claim 1  wherein a packet format of the at least one receive packet and the at least one transmit packet is compliant with at least one of the Institute of Electrical and Electronic Engineers  802 . 3  family of Ethernet standards.  
     
     
         4 . The data communications device of  claim 1  further comprising at least one optical carrier framer for performing transmit framing on data from at least one transmit data channel producing a transmit data sequence, and for performing receive framing on a receive data sequence producing data for at least one receive data channel.  
     
     
         5 . The data communication device of  claim 4  wherein the packet mapper is compatible with the American National Standards Institute T1X1.5 Generic Framing Procedure.  
     
     
         6 . The data communication device of  claim 4  wherein the packet mapper is compatible with the International Telecommunications Union X.86 Ethernet over SONET recommendation.  
     
     
         7 . The data communication device of  claim 4  wherein the packet mapper is compatible with the Internet Engineering Task Force RFC 1662 point-to-point protocol specification.  
     
     
         8 . The data communications device of  claim 4 , wherein a format of the transmit data sequence and the receive data sequence is compatible with the Synchronous Optical Network or Synchronous Digital Hierarchy optical carrier standard.  
     
     
         9 . The data communication device of  claim 1  further comprising a bus interface for connecting additional communications interface devices.  
     
     
         10 . The data communication device of  claim 9 , wherein the bus interface is a telecom bus compatible interface.  
     
     
         11 . The data communication device  claim 1  wherein the at least one communication interface comprises at least one T/E carrier framer for receiving and transmitting data in time division multiplexed format.  
     
     
         12 . The data communication device of  claim 11  wherein the at least one T/E carrier framer comprises a DS1 or E1 format framer.  
     
     
         13 . The data communication device of  claim 11  wherein the at least one T/E carrier framer comprises a DS3 or E3 format framer.  
     
     
         14 . The data communication device of  claim 12  further comprising a M13 multiplexer for converting DS1 format time division multiplex data streams to and from DS3 format.  
     
     
         15 . The data communication device of  claim 1  further comprising at least one embedded microprocessor core arranged in order receive signals from the hashing processor.  
     
     
         16 . The data communication device of  claim 15 , further comprising an embedded memory for storing information to be accessed by the at least one embedded microprocessor core.  
     
     
         17 . The data communication device of  claim 15  further comprising an external memory interface arranged to allow the at least one embedded microprocessor core to access information stored in an external memory device.  
     
     
         18 . The data communication device of  claim 1  wherein the functionality is contained within a single integrated circuit.  
     
     
         19 . A method of operating a data communication device, the method comprising: 
 receiving a first packet from a first packet stream at a higher bit rate;    selecting a first data link from a predefined group of data links;    depacketizing the first packet to a first data stream;    transmitting the first data stream on the first data link at a lower bit rate;    receiving a second data stream on a second data link at the lower bit rate;    packetizing the second data stream into a second packet;    designating a second packet stream on which to send the second packet; and    transmitting the second packet on the second packet stream at the higher bit rate.    
     
     
         20 . The method of  claim 19  wherein a packet format of the first packet stream and the second packet stream is compliant with at least one of the Institute of Electrical and Electronic Engineers 802.3 family of Ethernet standards.  
     
     
         21 . The method of  claim 19  wherein the first data link and the second data link use a time division multiplex format.  
     
     
         22 . The method of  claim 21  wherein the time division multiplex format is DS1 or E1 compliant.  
     
     
         23 . The method of  claim 19  wherein the first data link and the second data link are a type of digital subscriber line.  
     
     
         24 . A machine-readable storage, having stored thereon a computer program having a plurality of code sections for implementing a data communication device, the code sections executable by a machine for causing the machine to perform the operations comprising: 
 receiving a first packet from a first packet stream at a higher bit rate;    selecting a first data link from a predefined group of data links;    depacketizing the first packet to a first data stream;    transmitting the first data stream on the first data link at a lower bit rate;    receiving a second data stream on a second data link at the lower bit rate;    packetizing the second data stream into a second packet;    designating a second packet stream on which to send the second packet; and    transmitting the second packet on the second packet stream at the higher bit rate.    
     
     
         25 . The machine-readable storage of  claim 24  wherein a packet format of the first packet stream and the second packet stream is compliant with at least one of the Institute of Electrical and Electronic Engineers 802.3 family of Ethernet standards.  
     
     
         26 . The machine-readable storage of  claim 24  wherein the first data link and the second data link use a time division multiplex format.  
     
     
         27 . The machine-readable storage of  claim 26  wherein the time division multiplex format is DS1 or E1 compliant.  
     
     
         28 . The machine-readable storage of  claim 24  wherein the first data link and the second data link are a type of digital subscriber line.

Join the waitlist — get patent alerts

Track US2004076166A1 — get alerts on status changes and closely related new filings.

We store only your email — no account needed. See our privacy policy.