Semiconductor device and its manufacturing method

Abstract

A non-volatile semiconductor memory device which simultaneously possesses a non-volatile memory cell region which possesses an isolating insulation film which has been formed selectively within a semiconductor substrate, which also possesses a first electroconductive film (floating gate electrode) via a first gate insulating film which has been formed on the semiconductor substrate surface, and which also possesses a metal film (control gate electrode) via a second gate insulating film which has been formed above said electroconductive film and a peripheral transistor region which possesses a metal film (gate electrode) via a third gate insulating film which has been formed above the semiconductor substrate surface.

What is claimed is:  
     
         1 . A semiconductor device, comprising: 
 a double gate-type non-volatile memory cell which includes a first gate layer obtained by laminating a floating gate electrode, a control gate electrode of an electroconductor via an intermediate insulating film and a first gate side wall film which constitutes the side wall of said first gate layer;    a peripheral transistor which includes a second gate layer of said electroconductor and a second gate side wall film which constitutes the side wall of said second gate layer;    a first gate insulating film which is formed in such a way that said double gate-type non-volatile memory cell and said peripheral transistor are buried in it and whose surface has been planarized in a level fashion vis-à-vis said double gate-type non-volatile memory cell and peripheral transistor.    
     
     
         2 . The semiconductor device according to  claim 1 , wherein an isolating insulation film whose surface is virtually continuous and level with the surface of a semiconductor substrate is formed within said semiconductor substrate between said double gate-type non-volatile memory cell and said peripheral transistor.  
     
     
         3 . The semiconductor device according to either claims  1  or  2 , wherein said intermediate insulating film and said first gate insulating film are configured beneath said first gate layer and are comprised from an identical material at an identical thickness.  
     
     
         4 . The semiconductor device according to either claims  1  or  2 , wherein said intermediate insulating film and said first gate insulating film are configured beneath said first gate layer and are comprised from different materials at different thicknesses.  
     
     
         5 . The semiconductor device according to either claims  1  or  2 , wherein said electroconductor is a metal.  
     
     
         6 . The semiconductor device according to either claims  1  or  2 , wherein said floating gate electrode is comprised from polycrystalline silicon and wherein said control gate electrode and said second gate layer are comprised from metals.  
     
     
         7 . The semiconductor device according to either claims  1  or  2 , further comprising a memory cell region which includes said double gate-type non-volatile memory cell and a peripheral transistor region which includes said peripheral transistor while they are isolated and defined by said isolating insulation film and wherein the thickness of said control gate electrode in said memory cell region exceeds the thickness of said control gate electrode above said isolating insulation film.  
     
     
         8 . A method for manufacturing a semiconductor device, said method comprising the following steps: 
 (a) a step whereby a dummy gate pattern which consists of multiple layers and which possesses a first electroconductive layer as the lowermost layer is formed on a memory cell region and a peripheral transistor region which has been defined above a semiconductor substrate,    (b) a step whereby a coating film which covers said dummy gate pattern is formed;    (c) a step whereby said coating film is dry-etched in such a way that a gate side wall film will selectively remain on the side plane of said dummy gate pattern;    (d) a step whereby an interlayer insulating film is formed blanketwise on the remainder of the structure formed through the preceding processes;    (e) a step whereby the surface of said interlayer insulating film is etched back based on the chemical mechanical polish method until the surface of said intermediate insulating film and the surface of said dummy gate pattern become virtually continuous and flat;    (f) a step whereby said dummy gate pattern is partially removed in such a way that said dummy gate pattern will be removed from said peripheral transistor region but will remain in said memory cell region and that said gate side wall film will remain in both said memory cell region and said peripheral transistor region;    (g) a step whereby a second electroconductive layer is formed blanketwise on the remainder of the structure which has been formed through the preceding processes and which includes the region from which said dummy gate pattern has been removed; and    (h) a step whereby the surface of said interlayer insulating film is etched back based on the chemical mechanical polish method until the surface of said interlayer insulating film and the surface of said second electroconductive layer become virtually continuous and planarized.    
     
     
         9 . The method for manufacturing a semiconductor device according to  claim 8 , wherein a film which possesses an upper silicon layer and a lower silicon layer which sandwich an insulating film is formed as said dummy gate pattern in said process (a), and wherein 
 said step (c) is implemented in such a way that said insulating film will remain and that said upper silicon layer will be removed.    
     
     
         10 . The method for manufacturing a semiconductor device according to  claim 8 , furthering comprising the step of a process whereby an intermediate insulating film is formed above said first electroconductive layer between sad steps (e) and (f).