Parallel processor architecture

Abstract

A parallel hardware-based multithreaded processor is described. The processor includes a general purpose processor that coordinates system functions and a plurality of microengines that support multiple hardware threads. The processor also includes a memory control system that has a first memory controller that sorts memory references based on whether the memory references are directed to an even bank or an odd bank of memory and a second memory controller that optimizes memory references based upon whether the memory references are read references or write references.

What is claimed is:  
     
         1 . A parallel hardware-based multithreaded processor comprises: 
 a general purpose processor that coordinates system functions; and    a plurality of microengines that support multiple hardware threads.    
     
     
         2 . The processor of  claim 1  wherein the general purpose processor load microcontrol programs in the plurality of microcontrol engines.  
     
     
         3 . The processor of  claim 1  further comprising a memory control system.  
     
     
         4 . The processor of  claim 1  wherein the memory control system comprises a synchronous dynamic random access memory controller that sorts memory references based on whether the memory references are directed to an even bank or an odd bank of memory.  
     
     
         5 . The processor of  claim 1  wherein the memory control system comprises a static random access memory controller that optimizes memory references based upon whether the memory references are read references or write references.  
     
     
         6 . The processor of  claim 1  wherein each of the plurality of microengines employ hardware-based context swapping amongst a plurality of threads that are independently executable within each of the microengines.  
     
     
         7 . The processor of  claim 1  further comprising a high speed bus interface that couples the processor to a communication bus.  
     
     
         8 . The processor of  claim 1  further comprising a bus interface that couples the processor to a computer system bus.  
     
     
         9 . The processor of  claim 1  further comprising an internal bus arrangement to couple shared resources in the processor to the plurality of microengines.  
     
     
         10 . The processor of  claim 9  wherein the internal bus arrangement to couple shared resources, comprises: 
 a first bus to couple the general purpose processor to the plurality of microengines.  
 
     
     
         11 . The processor of  claim 9  wherein the internal bus arrangement to couple shared resources, comprises: 
 a translator device that translates requests from the general purpose processor to the microengines; and  
 a first bus to couple the general purpose processor to the plurality of microengines.  
 
     
     
         12 . The processor of  claim 3  wherein the internal bus arrangement to couple shared resources, comprises: 
 a translator device that translates requests from the general purpose processor to the microengines; and  
 a first bus to couple the general purpose processor to the plurality of microengines; and  
 a second bus to couple the general purpose processor to the memory control system.  
 
     
     
         13 . The processor of  claim 11 , further comprising a third bus to couple the microengines to external bus interfaces.  
     
     
         14 . The processor of  claim 8  wherein the shared resources comprise: 
 a memory controller for controlling access to low latency memory;  
 a memory controller for controlling an access to high bandwidth memory;  
 a bus interface for controlling access to a communications bus; and  
 a bus interface for controlling access to a computer bus.  
 
     
     
         15 . The processor of  claim 1  wherein each one of the microengines includes a program counter to uniquely identify a position of a thread during execution in the microengine.  
     
     
         16 . The processor of  claim 1  wherein the processor supports global signaling to each of the microengines.  
     
     
         17 . The processor of  claim 16  wherein the global signaling is available to each thread in each microengine.  
     
     
         18 . The processor of  claim 17  wherein the global signaling is available to each thread to permit each thread to take a branch.  
     
     
         19 . A parallel hardware-based multithreaded processor comprises: 
 a general purpose processor that coordinates system functions;    a plurality of microengines that support multiple hardware threads;    a memory control system comprising:    a first memory controller that sorts memory references based on whether the memory references are directed to an even bank or an odd bank of memory; and    a second memory controller that optimizes memory references based upon whether the memory references are read references or write references.    
     
     
         20 . The parallel hardware-based multithreaded processor of  claim 19  wherein the first memory controller controls synchronous dynamic random access memory and the second memory controller controls static random access static memory.