Integrated circuit metal-insulator-metal capacitors including hemispherical grain lumps

Abstract

The effective area of a MIM capacitor is increased by forming a lower electrode that includes hemispherical grain lumps. The hemispherical grain lumps are formed by heat-treating a metal layer in an oxygen and/or nitrogen atmosphere, thus oxidizing the surface of the metal layer or growing the crystal grains of the metal layer. The MIM capacitor may be formed of Pt, Ru, Rh, Os, Ir, or Pd, and the hemispherical grain lumps may be formed of Pt, Ru, Rh, Os, Ir, or Pd. Since the metal layer is primarily heat-treated during the formation of the lower electrode, it is possible to reduce the degree to which the surface morphology of the lower electrode is rapidly changed due to a heat treatment subsequent to forming a dielectric layer and an upper electrode.

What is claimed is:  
     
         1 . An integrated circuit capacitor comprising: 
 a lower electrode on an integrated circuit substrate, the lower electrode comprising a metal layer on the integrated circuit substrate and hemispherical grain lumps that protrude from the metal layer opposite the integrated circuit substrate;    a dielectric layer on the hemispherical grain lumps opposite the integrated circuit substrate; and    an upper electrode on the dielectric layer opposite the lower electrode;    wherein the metal layer and the hemispherical grain lumps comprise at least one of Pt, Ru, Rh, Os, Ir and Pd.    
     
     
         2 . The capacitor of  claim 1 , wherein the dielectric layer comprises at least one of Ta 2 O 5 , SrTiO 3 (STO), (Ba, Sr)TiO 3 (BST), PbTiO 3 , Pb(Zr, Ti)O 3 (PZT), SrBi 2 Ta 2 O 5 (SBT), (Pb, La)(Zr, Ti)O 3 , Bi 4 Ti 3 O 12 , or BaTiO 3 (BTO).  
     
     
         3 . The capacitor of  claim 1 , wherein the metal layer comprises a first portion and a second portion on the first portion, and wherein the first and second portions comprise different metals.  
     
     
         4 . The capacitor of  claim 3 , wherein the first portion comprises at least one of TaN, Ti, and TiN.  
     
     
         5 . The capacitor of  claim 4 , wherein the second portion comprises at least one of Pt, Ru, Rh, Os, Ir and Pd.  
     
     
         6 . The capacitor of  claim 4 , wherein the first portion comprises a first material, and wherein the second portion comprises a second material that is more readily oxidized than the first material, under same oxidizing conditions.  
     
     
         7 . The capacitor of claim  3 i wherein the first portion comprises Pt, and wherein the second portion comprises at least one of Ru, Rh, Os and Pd.  
     
     
         8 . The capacitor of  claim 1 , wherein the metal layer comprises a first portion and a second portion on the first portion, which both comprise a same metal, and wherein the first portion retains it surface morphology when forming the hemispherical grain lumps.  
     
     
         9 . The capacitor of  claim 8 , wherein the metal layer comprises at least one of Pt, Ru, Rh, Os, Ir and Pd.  
     
     
         10 . The capacitor of  claim 1 , wherein the lower electrode further comprises a metal layer on the integrated circuit substrate between the hemispherical grain lumps or the substrate and the metal layer, and the metal layer is sufficiently thin so as to maintain the profile of the hemispherical grain lumps.  
     
     
         11 . The capacitor of  claim 10 , wherein the hemispherical grain lumps comprise at least one of Pt, Ru, Rh, Os, Ir and Pd.  
     
     
         12 . The capacitor of  claim 10  wherein the hemispherical grain lumps comprise at least one of Ru, Rh, Os, Ir and Pd.  
     
     
         13 . The capacitor of  claim 1 , wherein the lower electrode comprises a metal layer on the substrate and a metal oxide layer on the metal layer opposite the substrate, and the hemispherical grain lumps protrude from the metal oxide layer opposite the metal layer.  
     
     
         14 . The capacitor of  claim 13 , wherein the metal layer comprises at least one of Pt, Ru, Rh, Os, Ir and Pd.  
     
     
         15 . An integrated circuit capacitor comprising: 
 a lower electrode on an integrated circuit substrate, the lower electrode comprising a metal layer on the integrated circuit substrate and hemispherical grain lumps that comprises at least one noble metal and that protrude from the metal layer opposite the integrated circuit substrate;    a dielectric layer on the hemispherical grain lumps that comprise at least one noble metal, opposite the integrated circuit substrate; and    an upper electrode on the dielectric layer opposite the lower electrode.    
     
     
         16 . The capacitor of  claim 15 , wherein the metal layer comprises a first portion and a second portion on the first portion, and wherein the first and second portions comprise different metals.  
     
     
         17 . The capacitor of  claim 16 , wherein the first portion comprises at least one of TaN, Ti, and TiN.  
     
     
         18 . The capacitor of  claim 17 , wherein the second portion comprises at least one of Pt, Ru, Rh, Os, Ir and Pd.