US2004062627A1PendingUtilityA1
System for the improved handling of wafers within a process tool
Priority: Sep 27, 2002Filed: Sep 17, 2003Published: Apr 1, 2004
Est. expirySep 27, 2022(expired)· nominal 20-yr term from priority
H10P 72/3412H10P 72/3411Y10S414/135Y10S414/137Y10S414/14
39
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Claims
Abstract
A substrate fabrication system is provided which includes a buffer station located inline between a front docking port and a loadlock chamber, the buffer station being operatively joined with a front handling chamber. Preferred embodiments employ a buffer station having a rack with reduced pitch, or relative spacing between shelves. Additional embodiments provide variable pitch end effectors as part of the disclosed fabrication system.
Claims
exact text as granted — not AI-modifiedWe claim:
1 . A semiconductor processing tool comprising:
a first substrate handling chamber; a front docking port located on the outside surface of the first substrate chamber; a robot arm located in the front wafer handling chamber; a loadlock chamber joined to the first substrate handling chamber; and a buffer station located between the loadlock chamber and the front docking ports, the buffer station being configured to provide a less contaminated inert internal environment as compared with the internal environment of a cassette docked to the docking port, the buffer station having a rack configured to have multiple shelves for holding substrates.
2 . The semiconductor processing tool according to claim 1 , wherein the rack is configured to support a plurality of 300 mm silicon wafers.
3 . The semiconductor processing tool according to claim 1 , further comprising a rear substrate handling chamber, where the loadlock chamber is located between the first substrate handling chamber and the rear substrate handling chamber.
4 . The semiconductor processing tool according to claim 1 , wherein the buffer station is further configured to create an inert environment which is selectively isolated from the first substrate handling chamber.
5 . The semiconductor processing tool according to claim 4 , wherein the buffer station is further configured to be selectively purged.
6 . The semiconductor processing tool according to claim 4 , wherein the buffer station rack is configured to allow the robot arm to be capable of accessing the entire buffer station rack through the use of a z-motion of the robot arm.
7 . The semiconductor processing tool according to claim 1 , wherein the buffer station is configured to have a internal volume less than or equal to about 18.3 liters.
8 . The semiconductor processing tool according to claim 7 , wherein the buffer station rack is configured to support twenty-five 300 mm silicon wafers.
9 . The semiconductor processing tool according to claim 1 , wherein the loadlock chamber is configured to have a internal volume less than or equal to about 9.156 liters.
10 . The semiconductor processing tool according to claim 1 , wherein the shelves of the buffer station rack have a reduced pitch relative to a front opening unified pod (FOUP) for the same size substrates.
11 . The semiconductor processing tool according to claim 1 , wherein the robot arm is configured to employ a variable pitch end effector having multiple end effector shelves.
12 . The semiconductor processing tool according to claim 1 , wherein the first substrate handling chamber is configured to operate at atmospheric pressure.
13 . The semiconductor processing tool according to claim 1 , wherein the first substrate handling chamber is configured to operate at reduced pressure.
14 . A semiconductor processing tool comprising:
a substrate handling chamber; a front docking port located on an outside surface of the substrate handling chamber, the port being capable of mating with a cassette; a cassette rack internal to the docked cassette; a purgeable buffer station joined with the substrate handling chamber, the buffer station being located in position downstream of the front docking port; and a buffer station rack within the buffer station being configured to have multiple slots for holding substrates.
15 . The semiconductor processing tool according to claim 14 , further comprising a loadlock chamber joined with the substrate handling chamber, the loadlock chamber having a loadlock rack with a substrate capacity of less than one third of a substrate capacity of the cassette.
16 . The semiconductor processing tool according to claim 15 , further comprising a rear substrate handling chamber where the loadlock chamber is located between the substrate handling chamber and the rear substrate handling chamber.
17 . The semiconductor processing tool according to claim 15 , wherein the substrate capacity of the loadlock chamber is 1 to 7 substrates.
18 . The semiconductor processing tool according to claim 15 , wherein the loadlock rack is configured to support a plurality of 300 mm silicon wafers.
19 . The semiconductor processing tool according to claim 14 , wherein the substrate handling chamber is configured to operate at standard atmospheric pressure.
20 . The semiconductor processing tool according to claim 14 , wherein the substrate handling chamber is configured to operate at reduced pressure.
21 . The semiconductor processing tool according to claim 14 , wherein the buffer station rack has a reduced relative spacing between the rack slots as compared with a relative spacing between slots of the cassette.
22 . The semiconductor processing tool according to claim 14 , wherein the buffer station rack is a reduced pitch rack configured to allow a robot arm to be capable of accessing the entire buffer station rack through the use of a robot arm's z-motion.
23 . The semiconductor processing tool according to claim 14 , further comprising a robot arm configured to have a variable pitch end effector designed to transfer multiple substrates from the cassette rack to the buffer station rack, the cassette rack having unequal slot pitch relative to the buffer station rack.Join the waitlist — get patent alerts
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