Method and structure for tungsten gate metal surface treatment while preventing oxidation

Abstract

As disclosed herein, an FEOL line conductor stack is formed including a base conductor layer, an overlying layer of tungsten, and an optional gate capping layer. The stack, including layers from the optional capping layer down to the base conductor layer are directionally etched until an underlying layer is exposed. Then, the substrate is exposed to one or the other or both of: 1) a silicon-containing ambient to form a self-aligned layer of tungsten silicide on sidewalls of the tungsten layer; and 2) a source of nitrogen to form a thin layer of tungsten nitride on sidewalls of the tungsten layer. Such tungsten silicide and/or tungsten nitride layers serves to protect the tungsten during subsequent processing, among which may include sidewall oxidation (e.g. for a polysilicon base conductor layer) and/or the forming of silicon nitride spacers on sidewalls of the gate stack.

What is claimed is:  
     
         1 . In an integrated circuit, a method of forming a low resistance FEOL conductive line stack comprising: 
 over an underlying layer on a semiconductor substrate, forming a stack including at least a base conductor layer and a layer of tungsten overlying said base conductor layer;    etching said stack through said tungsten layer to at least expose a top of said base conductor layer; and    heating said substrate after exposing said substrate to at least one of: 1) a silicon-containing ambient to thereby form a self-aligned layer of tungsten silicide on sidewalls of said tungsten layer; and 2) a source of nitrogen to thereby form a thin layer of tungsten nitride on sidewalls of said tungsten layer.    
     
     
         2 . The method of  claim 1  wherein said etching stops when a top of said base conductor layer is reached, and said etching is continued through said base conductor layer after said self-aligned tungsten silicide layer is formed.  
     
     
         3 . The method of  claim 1  wherein said base conductor layer comprises polysilicon and said base conductor layer contacts a gate dielectric formed on a semiconductor substrate.  
     
     
         4 . The method of  claim 1  wherein said silicon-containing ambient includes a gas selected from the group consisting of mono-silane, di-silane, and dichlorsilane.  
     
     
         5 . The method of  claim 1  wherein said source of nitrogen includes a gas selected from the group consisting of ammonia, ionized nitrogen, nitric oxide, and nitrous oxide.  
     
     
         6 . The method of  claim 1  wherein said etching is stopped when said base conductor layer is exposed, prior to exposing said substrate to said silicon-containing ambient.  
     
     
         7 . The method of  claim 6  wherein a layer of silicon is deposited over said partially etched stack from said silicon-containing ambient, and thereafter said substrate is heated to form said self-aligned tungsten silicide, said base conductor layer then being etched through to said underlying layer, thereby removing said layer of deposited silicon from said etched stack.  
     
     
         8 . The method of  claim 1  wherein said stack includes a capping layer formed over said tungsten layer.  
     
     
         9 . The method of  claim 8  wherein said capping layer includes silicon nitride.  
     
     
         10 . The method of  claim 2  further comprising oxidizing sidewalls of said polysilicon layer.  
     
     
         11 . The method of  claim 10  wherein said oxidizing is performed by heating said substrate in an oxygen-containing ambient.  
     
     
         12 . In an integrated circuit, a method of fabricating tungsten gate conductors, comprising 
 providing a gate stack including polysilicon layer over a gate dielectric on a substrate, a tungsten layer over said polysilicon layer, and a capping layer over said tungsten layer;    etching said gate stack down to said gate dielectric;    performing at least one of nitriding and siliciding sidewalls of said exposed tungsten layer; and    thereafter exposing said gate stack to oxygen to form an oxide on sidewalls of said polysilicon layer.    
     
     
         13 . The method of  claim 12 , wherein said capping layer is comprised of silicon nitride.  
     
     
         14 . An integrated circuit including an FEOL conductive line stack, comprising: 
 a base conductor layer; and    a layer of tungsten overlying said polysilicon layer;    wherein said tungsten layer includes sidewalls having at least one of a self-aligned tungsten silicide, a self-aligned tungsten nitride, or a self-aligned tungsten oxynitride.    
     
     
         15 . The integrated circuit of  claim 14  wherein said base conductor layer comprises polysilicon, and said base conductor layer includes oxidized sidewalls.