Gate with dual gate dielectric layer and method of fabricating the same

Abstract

A gate with dual gate dielectric layer and fabrication method thereof. A semiconductor substrate is provided, on which a dielectric layer and a patterned hard mask layer with an opening are sequentially formed. A spacer is formed on a sidewall of the opening. The semiconductor substrate is ion implanted, the spacer and the exposed dielectric layer are removed, and a gate oxide layer is formed on the bottom of the opening.

What is claimed is:  
     
         1 . A method for fabricating a gate with dual gate dielectric layer, comprising: 
 providing a semiconductor substrate, with a dielectric layer and a patterned hard mask layer with an opening sequentially formed thereon;    forming a spacer on a sidewall of the opening;    implanting nitrogen ions into the semiconductor substrate;    removing the spacer and the exposed dielectric layer; and    forming a gate oxide layer on a bottom of the opening.    
     
     
         2 . The method for fabricating a gate with dual gate dielectric layer as claimed in  claim 1 , further comprising: 
 filling a conducting layer in the opening; and    removing the hard mask layer.    
     
     
         3 . The method for fabricating a gate with dual gate dielectric layer as claimed in  claim 1 , wherein the dielectric layer is a pad oxide layer.  
     
     
         4 . The method for fabricating a gate with dual gate dielectric layer as claimed in  claim 1 , wherein the patterned hard mask layer comprises a nitride layer.  
     
     
         5 . The method for fabricating a gate with dual gate dielectric layer as claimed in  claim 1 , wherein a method for forming the gate oxide layer comprises thermal oxidation.  
     
     
         6 . The method for fabricating a gate with dual gate dielectric layer as claimed in  claim 1 , wherein the conducting layer comprises a polysilicon layer or an exi-silicon layer.  
     
     
         7 . A method for fabricating a gate with dual gate dielectric layer, comprising: 
 providing a semiconductor substrate, with a dielectric layer, a hard mask layer, and a patterned photoresist layer with a first opening sequentially formed thereon, wherein the first opening exposes the hard mask layer;    etching the hard mask layer to form a second opening using the patterned photoresist layer as a mask;    removing the patterned photoresist layer;    conformally forming an insulating layer over the hard mask layer and the second opening;    anisotropically etching the insulating layer to form a spacer on a sidewall of the second opening;    implanting nitrogen ions into the exposed semiconductor substrate using the hard mask layer and the spacer as masks;    removing the spacer and the exposed dielectric layer; and    thermally oxidizing the semiconductor substrate to form a gate oxide layer over a bottom of the second opening using the hard mask layer as a mask.    
     
     
         8 . The method for fabricating a gate with dual gate dielectric layer as claimed in  claim 7 , further comprising: 
 forming a conducting layer over the hard mask layer, the second opening filled with the conducting layer;    planarizing the conducting layer to expose the hard mask layer; and    removing the hard mask layer.    
     
     
         9 . The method for fabricating a gate with dual gate dielectric layer as claimed in  claim 7 , wherein the dielectric layer comprises a pad oxide layer.  
     
     
         10 . The method for fabricating a gate with dual gate dielectric layer as claimed in  claim 7 , wherein the hard mask layer comprises a nitride layer.  
     
     
         11 . The method for fabricating a gate with dual gate dielectric layer as claimed in  claim 7 , wherein the insulating layer comprises an oxide layer.  
     
     
         12 . The method for fabricating a gate with dual gate dielectric layer as claimed in  claim 7 , wherein the method of anisotropic etching comprises a reactive ion etching or a plasma etching.  
     
     
         13 . The method for fabricating a gate with dual gate dielectric layer as claimed in  claim 7 , wherein the conducting layer comprises a polysilicon layer or an exi-silicon layer.  
     
     
         14 . The method for fabricating a gate with dual gate dielectric layer as claimed in  claim 7 , wherein the method of planarizing comprises chemical mechanical polishing.  
     
     
         15 . A gate with dual gate dielectric layer, comprising: 
 a dual gate dielectric layer, formed over a semiconductor substrate, comprising an inner portion and a outer portion, wherein the inner portion is thinner than the outer portion; and    a conducting layer, formed on the dual gate dielectric layer.    
     
     
         16 . The gate with dual gate dielectric layer as claimed in  claim 15 , wherein the dual gate dielectric layer comprises a gate oxide layer.  
     
     
         17 . A gate with dual gate dielectric layer, comprising: 
 a semiconductor substrate;    a dual gate dielectric layer, formed over the semiconductor substrate, comprising a first gate dielectric layer and a second gate dielectric layer, wherein the second gate dielectric layer is formed in an inner portion of the first gate dielectric layer, and the second gate dielectric layer is thinner than the first gate dielectric layer; and    a conducting layer, formed on the dual gate dielectric layer.    
     
     
         18 . The gate with dual gate dielectric layer as claimed in  claim 17 , wherein the first gate dielectric layer comprises a gate oxide layer.  
     
     
         19 . The gate with dual gate dielectric layer as claimed in  claim 17 , wherein the second gate dielectric layer comprises a gate oxide layer.