Method and apparatus for promoting memory read commands

Abstract

A device for providing data includes a data source, a bus interface, a data buffer, and control logic. The bus interface is coupled to a plurality of control lines of a bus and adapted to receive a read request targeting the data source. The control logic is adapted to determine if the read request requires multiple data phases to complete based on the control lines, and to retrieve at least two data phases of data from the data source and store them in the data buffer in response to the read request requiring multiple data phases to complete. A method for retrieving data includes receiving a read request on a bus. The bus includes a plurality of control lines. It is determined if the read request requires multiple data phases to complete based on the control lines. At least two data phases of data are retrieved from a data source in response to the read request requiring multiple data phases to complete. The at least two data phases of data are stored in a data buffer.

What is claimed:  
     
         1 . A bridge device for communicating between a first and a second bus, comprising: 
 a bus interface coupled to a plurality of control lines of the first bus and adapted to receive a read request targeting the second bus;    a data buffer; and    control logic adapted to determine if the read request requires multiple data phases to complete based on the control lines, and to retrieve at least two data phases of data from the second bus and store them in the data buffer in response to the read request requiring multiple data phases to complete.    
     
     
         2 . The bridge device of  claim 1 , wherein the control lines include a stop line, and the control logic is adapted to assert a stop signal on the stop line after determining that the read request requires multiple data phases.  
     
     
         3 . The bridge device of  claim 1 , wherein the control lines include a frame line and a initiator ready line, and the control logic is adapted to sample a frame signal on the frame line and an initiator ready signal on the initiator ready line to determine of the read request requires multiple data phases.  
     
     
         4 . The bridge device of  claim 3 , wherein the control logic is adapted to determine that the read request requires multiple data phases in response to the frame signal and the initiator ready signal being asserted concurrently.  
     
     
         5 . The bridge device of  claim 4 , wherein the control logic is adapted to determine that the read request requires multiple data phases in response to the frame signal and the initiator ready signal being asserted concurrently within a predetermined number of clock cycles.  
     
     
         6 . The bridge device of  claim 5 , wherein the control logic is adapted to retrieve only one phase of data in response to the frame signal and the initiator ready signal not being asserted concurrently within the predetermined number of clock cycles.  
     
     
         7 . The bridge device of  claim 4 , wherein the control logic is adapted to sample the frame signal and the initiator ready signal in response to the initiator ready signal being asserted.  
     
     
         8 . The bridge device of  claim 7 , wherein the control logic is adapted to retrieve only one phase of data in response to the frame signal and the initiator ready signal not being asserted concurrently when the initiator ready signal is asserted.  
     
     
         9 . The bridge device of  claim 3 , wherein the control lines include a stop line, and the control logic is adapted assert a stop signal on the stop line in response to data corresponding to the read request not being stored in the data buffer.  
     
     
         10 . The bridge device of  claim 9 , wherein the control logic is adapted to sample the frame signal and the initiator signal when asserting the stop signal.  
     
     
         11 . The bridge device of  claim 10 , wherein the control logic is adapted to retrieve only one phase of data in response to the frame signal and the initiator ready signal not being asserted concurrently when the stop signal is asserted.  
     
     
         12 . The bridge device of  claim 1 , wherein the control logic is adapted to retrieve a plurality of data phases of data in response to the read request requiring multiple data phases until a cache line boundary is reached.  
     
     
         13 . The bridge device of  claim 1 , wherein the control logic is adapted to retrieve a plurality of data phases of data in response to the read request requiring multiple data phases until the data buffer is full.  
     
     
         14 . The bridge device of  claim 5 , wherein the predetermined number of cycles is between two and five.  
     
     
         15 . The bridge device of  claim 5 , wherein the predetermined number of cycles is at least two.  
     
     
         16 . A device for providing data, comprising: 
 a data source;    a bus interface coupled to a plurality of control lines of a bus and adapted to receive a read request targeting the data source;    a data buffer; and    control logic adapted to determine if the read request requires multiple data phases to complete based on the control lines, and to retrieve at least two data phases of data from the data source and store them in the data buffer in response to the read request requiring multiple data phases to complete.    
     
     
         17 . The device of  claim 16 , wherein the control lines include a stop line, and the control logic is adapted to assert a stop signal on the stop line after determining that the read request requires multiple data phases.  
     
     
         18 . The device of  claim 16 , wherein the control lines include a frame line and a initiator ready line, and the control logic is adapted to sample a frame signal on the frame line and an initiator ready signal on the initiator ready line to determine of the read request requires multiple data phases.  
     
     
         19 . The device of  claim 18 , wherein the control logic is adapted to determine that the read request requires multiple data phases in response to the frame signal and the initiator ready signal being asserted concurrently.  
     
     
         20 . The device of  claim 19 , wherein the control logic is adapted to determine that the read request requires multiple data phases in response to the frame signal and the initiator ready signal being asserted concurrently within a predetermined number of clock cycles.  
     
     
         21 . The device of  claim 20 , wherein the control logic is adapted to retrieve only one phase of data in response to the frame signal and the initiator ready signal not being asserted concurrently within the predetermined number of clock cycles.  
     
     
         22 . The device of  claim 19 , wherein the control logic is adapted to sample the frame signal and the initiator ready signal in response to the initiator ready signal being asserted.  
     
     
         23 . The device of  claim 22 , wherein the control logic is adapted to retrieve only one phase of data in response to the frame signal and the initiator ready signal not being asserted concurrently when the initiator ready signal is asserted.  
     
     
         24 . The device of  claim 18 , wherein the control lines include a stop line, and the control logic is adapted assert a stop signal on the stop line in response to data corresponding to the read request not being stored in the data buffer.  
     
     
         25 . The device of  claim 24 , wherein the control logic is adapted to sample the frame signal and the initiator signal when asserting the stop signal.  
     
     
         26 . The device of  claim 25 , wherein the control logic is adapted to retrieve only one phase of data in response to the frame signal and the initiator ready signal not being asserted concurrently when the stop signal is asserted.  
     
     
         27 . The device of  claim 16 , wherein the control logic is adapted to retrieve a plurality of data phases of data in response to the read request requiring multiple data phases until a cache line boundary is reached.  
     
     
         28 . The device of  claim 16 , wherein the control logic is adapted to retrieve a plurality of data phases of data in response to the read request requiring multiple data phases until the data buffer is full.  
     
     
         29 . The device of  claim 16 , wherein the data source comprises at least one of a second bus, a disk drive, and a network.  
     
     
         30 . The device of  claim 20 , wherein the predetermined number of cycles is between two and five.  
     
     
         31 . The device of  claim 20 , wherein the predetermined number of cycles is at least two.  
     
     
         32 . A method for retrieving data, comprising: 
 receiving a read request on a bus, the bus including a plurality of control lines;    determining that the read request requires multiple data phases to complete based on the control lines;    retrieving at least two data phases of data from a data source in response to the read request requiring multiple data phases to complete; and    storing the at least two data phases of data in a data buffer.    
     
     
         33 . The method of  claim 32 , wherein the control lines include a stop line, and the method further includes asserting a stop signal on the stop line after determining that the read request requires multiple data phases.  
     
     
         34 . The method of  claim 32 , wherein the control lines include a frame line and a initiator ready line, and determining that the read request requires multiple data phases includes: 
 sampling a frame signal on the frame line; and    sampling an initiator ready signal on the initiator ready line.    
     
     
         35 . The method of  claim 34 , wherein determining that the read request requires multiple data phases includes determining that the frame signal and the initiator ready signal are asserted concurrently.  
     
     
         36 . The method of  claim 35 , wherein determining that the read request requires multiple data phases includes determining that the frame signal and the initiator ready signal are asserted concurrently within a predetermined number of clock cycles.  
     
     
         37 . The method of  claim 36 , further comprising retrieving only one phase of data in response to the frame signal and the initiator ready signal not being asserted concurrently within the predetermined number of clock cycles.  
     
     
         38 . The method of  claim 35 , wherein determining that the read request requires multiple data phases includes sampling the frame signal and the initiator ready signal in response to the initiator ready signal being asserted.  
     
     
         39 . The method of  claim 38 , further comprising retrieving only one phase of data in response to the frame signal and the initiator ready signal not being asserted concurrently when the initiator ready signal is asserted.  
     
     
         40 . The method of  claim 34 , wherein the control lines include a stop line, and the method further comprises asserting a stop signal on the stop line in response to data corresponding to the read request not being stored in the data buffer.  
     
     
         41 . The method of  claim 40 , wherein determining that the read request requires multiple data phases includes sampling the frame signal and the initiator signal when asserting the stop signal.  
     
     
         42 . The method of  claim 25 , further comprising retrieving only one phase of data in response to the frame signal and the initiator ready signal not being asserted concurrently when the stop signal is asserted.  
     
     
         43 . The method of  claim 32 , wherein retrieving the at least two data phases of data includes retrieving a plurality of data phases of data until a cache line boundary is reached.  
     
     
         44 . The method of  claim 32 , wherein retrieving the at least two data phases of data includes retrieving a plurality of data phases of data until the data buffer is full.  
     
     
         45 . The method of  claim 32 , wherein retrieving the at least two data phases of data from the data source includes retrieving the at least two data phases of data from at least one of a second bus, a disk drive, and a network.  
     
     
         46 . The method of  claim 36 , wherein determining that the frame signal and the initiator ready signal are asserted concurrently within a predetermined number of clock cycles includes determining that the frame signal and the initiator ready signal are asserted concurrently within between two and five clock cycles.  
     
     
         47 . The method of  claim 36 , wherein determining that the frame signal and the initiator ready signal are asserted concurrently within a predetermined number of clock cycles includes determining that the frame signal and the initiator ready signal are asserted concurrently within at least two clock cycles.  
     
     
         48 . A computer system, comprising: 
 a first bus having a plurality of control lines;    a second bus;    an initiating device coupled to the first bus and being adapted to initiate a read request targeting the target device;    a target device coupled to the second bus; and    a bridge device for communicating between the first and second buses, comprising: 
 a data buffer; and  
 control logic adapted to receive the read request, determine if the read request requires multiple data phases to complete based on the control lines, retrieve at least two data phases of data from the target device, and store the at least two data phases of data in the data buffer in response to the read request requiring multiple data phases to complete.  
   
     
     
         49 . The computer system of  claim 48 , wherein the control lines include a stop line, and the control logic is adapted to assert a stop signal on the stop line after determining that the read request requires multiple data phases.  
     
     
         50 . The computer system of  claim 48 , wherein the control lines include a frame line and a initiator ready line, the initiating device is adapted to assert a frame signal on the frame line and an initiator ready signal on the initiator ready line, and the control logic is adapted to sample the frame signal and the initiator ready signal to determine of the read request requires multiple data phases.  
     
     
         51 . The computer system of  claim 50 , wherein the control logic is adapted to determine that the read request requires multiple data phases in response to the frame signal and the initiator ready signal being asserted concurrently.  
     
     
         52 . The computer system of  claim 51 , wherein the control logic is adapted to determine that the read request requires multiple data phases in response to the frame signal and the initiator ready signal being asserted concurrently within a predetermined number of clock cycles.  
     
     
         53 . The computer system of  claim 52 , wherein the control logic is adapted to retrieve only one phase of data in response to the frame signal and the initiator ready signal not being asserted concurrently within the predetermined number of clock cycles.  
     
     
         54 . The computer system of  claim 51 , wherein the control logic is adapted to sample the frame signal and the initiator ready signal in response to the initiator ready signal being asserted.  
     
     
         55 . The computer system of  claim 54 , wherein the control logic is adapted to retrieve only one phase of data in response to the frame signal and the initiator ready signal not being asserted concurrently when the initiator ready signal is asserted.  
     
     
         56 . The computer system of  claim 50 , wherein the control lines include a stop line, and the control logic is adapted assert a stop signal on the stop line in response to data corresponding to the read request not being stored in the data buffer.  
     
     
         57 . The computer system of  claim 56 , wherein the control logic is adapted to sample the frame signal and the initiator signal when asserting the stop signal.  
     
     
         58 . The computer system of  claim 57 , wherein the control logic is adapted to retrieve only one phase of data in response to the frame signal and the initiator ready signal not being asserted concurrently when the stop signal is asserted.  
     
     
         59 . The computer system of  claim 48 , wherein the control logic is adapted to retrieve a plurality of data phases of data in response to the read request requiring multiple data phases until a cache line boundary is reached.  
     
     
         60 . The computer system of  claim 48 , wherein the control logic is adapted to retrieve a plurality of data phases of data in response to the read request requiring multiple data phases until the data buffer is full.  
     
     
         61 . The computer system of  claim 52 , wherein the predetermined number of cycles is between two and five.  
     
     
         62 . The computer system of  claim 52 , wherein the predetermined number of cycles is at least two.  
     
     
         63 . An apparatus, comprising: 
 means for receiving a read request on a bus, the bus including a plurality of control lines;    means for determining that the read request requires multiple data phases to complete based on the control lines;    means for retrieving at least two data phases of data from a data source in response to the read request requiring multiple data phases to complete; and    means for storing the at least two data phases of data.