Mosfet with short channel structure and formation method thereof

Abstract

A MOSFET with a short channel structure and manufacturing processes for the same are described. The MOSFET has a substrate, a channel region, a source/drain region, a gate dielectric layer and a conductive layer. The channel region in the substrate includes a first region and a second region, in which the first region has a first threshold voltage and the second region has a second threshold voltage, respectively. The first threshold voltage is smaller than the second threshold voltage. The first threshold voltage of the first region can also be adjusted to reduce or increase effectively the resistance of the MOSFET when the MOSFET is turned on or off. Additionally, the first region has a shallower junction depth than that of the normal source/drain extension.

What is claimed is:  
     
         1 . A method for forming a MOSFET with a short channel structure, the method comprising the steps of: 
 performing a first ion implantation into a substrate resulting in the substrate having a first threshold voltage;    forming a sacrificial layer on the substrate to define a channel region;    forming a source/drain on the substrate, wherein the source/drain are coupled to the channel region;    forming a first dielectric layer on the substrate and the sacrificial layer;    removing a portion of the first dielectric layer to expose the sacrificial layer;    removing the sacrificial layer to generate an opening in the first dielectric layer and to expose the channel region;    forming a second dielectric layer on the first dielectric layer and the channel region;    performing an anisotropic etching on the second dielectric layer to form a plurality of spacers adjacent to the opening, wherein a portion of the channel region of the substrate is defined as a first region and an exposed channel region;    performing a second ion implantation on the exposed channel region, resulting in the exposed channel region having a second threshold voltage and being defined as a second region;    removing the spacers of the first region, wherein the first threshold voltage of the first region is smaller than the second threshold voltage of the second region;    forming a gate dielectric layer on the channel region; and    forming a conductive layer on the gate dielectric layer and the first dielectric layer.    
     
     
         2 . The method of  claim 1 , wherein the first region is located between the second region and the source/drain to separate the second region and the source/drain.  
     
     
         3 . The method of  claim 1 , wherein the first ion implantation and the second ion implantation use a same dopant.  
     
     
         4 . The method of  claim 3 , wherein the same dopant comprises boron.  
     
     
         5 . The method of  claim 1 , wherein the first ion implantation has a doping concentration range of about 1×10 12  cm −2  to 3×10 13  cm −2 .  
     
     
         6 . The method of  claim 1 , wherein the second ion implantation has a doping concentration range of about 1×10 12  cm −2  to 3×10 13  cm −2 .  
     
     
         7 . The method of  claim 1 , wherein a material of the sacrificial layer comprises silicon nitrides or oxynitrides.  
     
     
         8 . The method of  claim 1 , wherein the sacrificial layer has a thickness range of about 600 to 3000 angstroms.  
     
     
         9 . A method for forming a MOSFET with a short channel structure, the method comprising the steps of: 
 forming a sacrificial layer on a substrate to define a channel region;    forming a source/drain on the substrate, wherein the source/drain are coupled to the channel region;    forming a first dielectric layer on the substrate and the sacrificial layer;    removing a portion of the first dielectric layer to expose the sacrificial layer;    removing the sacrificial layer to generate an opening in the first dielectric layer and to expose the channel region;    performing a first ion implantation into the substrate resulting in the substrate having a first threshold voltage;    forming a second dielectric layer on the first dielectric layer and the channel region;    performing an anisotropic etching on the second dielectric layer to form a plurality of spacers adjacent to the opening, wherein a portion of the channel region of the substrate is defined as a first region and an exposed channel region;    performing a second ion implantation on the exposed channel region, resulting in the exposed channel region having a second threshold voltage and being defined as a second region;    removing the spacers of the first region, wherein the first threshold voltage of the first region is smaller than the second threshold voltage of the second region;    forming a gate dielectric layer on the channel region; and    forming a conductive layer on the gate dielectric layer and the first dielectric layer.    
     
     
         10 . The method of  claim 9 , wherein the first region is located between the second region and the source/drain to separate the second region and the source/drain.  
     
     
         11 . The method of  claim 9 , wherein the first ion implantation and the second ion implantation use a same dopant.  
     
     
         12 . The method of  claim 11 , wherein the same dopant comprises boron.  
     
     
         13 . The method of  claim 9 , wherein the first ion implantation has a doping concentration range of about 1×10 12  cm −2  to 3×10 13  cm −2 .  
     
     
         14 . The method of  claim 9 , wherein the second ion implantation has a doping concentration range of about 1×10 12  cm −2  to 3×10 13  cm −2 .  
     
     
         15 . The method of  claim 9 , wherein a material of the sacrificial layer comprises silicon nitrides or oxynitrides.  
     
     
         16 . The method of  claim 9 , wherein the sacrificial layer has a thickness range of about 600 to 3000 angstroms.  
     
     
         17 . A MOSFET with a short channel structure, the MOSFET comprising: 
 a substrate;    a channel region positioned in the substrate and including a first region a second region, wherein the first region is coupled to the second region, the first region has a first threshold voltage and the second region has a second threshold voltage, and the first threshold voltage is smaller than the second threshold voltage;    a source/drain coupled to a sidewall of the channel region, wherein the first region is positioned between the second region and the source/drain to separate the second region and the source/drain;    a gate dielectric layer covering the channel region and being adjacent to the source/drain; and    a conductive layer covering the gate dielectric layer on the channel region.    
     
     
         18 . The MOSFET of  claim 17 , wherein the first region has a sufficiently low resistance when a gate of the MOSFET is turned on.  
     
     
         19 . The MOSFET of  claim 17 , wherein the first region has a sufficiently high resistance when a gate of the MOSFET is turned off.  
     
     
         20 . The MOSFET of  claim 17 , wherein the first threshold voltage is adjusted by a first ion implantation.  
     
     
         21 . The MOSFET of  claim 20 , wherein the first ion implantation has a concentration doping range of about 1×10 12  cm −2  to 3×10 3  cm −2 .  
     
     
         22 . The MOSFET of  claim 21 , wherein the second threshold voltage is adjusted by a second ion implantation.  
     
     
         23 . The MOSFET of  claim 22 , wherein the second ion implantation has a concentration doping range of about 1×10 12  cm −2  to 3×10 13  cm −2 .  
     
     
         24 . The MOSFET of  claim 21 , wherein the first ion implantation and the second ion implantation use a same dopant of electric type.  
     
     
         25 . The MOSFET of  claim 24 , wherein the same dopant comprises boron.  
     
     
         26 . The MOSFET of  claim 17 , wherein the gate dielectric layer has a thickness range of about 5 to 70 angstroms.