Extended register space apparatus and methods for processors

Abstract

Methods and apparatus for accessing an extended register space associated with a processor are disclosed. In an example method, a first portion of an encoding field of an instruction is compared to a value associated with the extended register space. A first operand of the instruction is associated with a second portion of the encoding field if the first portion of the encoding field matches the value associated with the extended register space.

What is claimed is:  
     
         1 . A method of accessing an extended register space associated with a processor, the method comprising: 
 comparing a first portion of a first encoding field of an instruction to a value associated with the extended register space; and    associating a first operand of the instruction with a second portion of the first encoding field if the first portion of the first encoding field matches the value associated with the extended register space.    
     
     
         2 . The method of  claim 1 , wherein comparing the first portion of the first encoding field to the value associated with the extended register space includes comparing a portion of a displacement field of the instruction to the value associated with the extended register space.  
     
     
         3 . The method of  claim 2 , wherein comparing the portion of the displacement field of the instruction to the value associated with the extended register space includes comparing a page identifier portion of the displacement field to a page identifier associated with the extended register space.  
     
     
         4 . The method of  claim 3 , wherein comparing the page identifier portion of the displacement field to the page identifier associated with the extended register space includes comparing a predetermined number of most significant bits of the displacement field to the page identifier associated with the extended register space.  
     
     
         5 . The method of  claim 1 , wherein associating the first operand of the instruction with the second portion of the first encoding field if the first portion of the first encoding field matches the value associated with the extended register space includes associating one of a source and a destination operand with the second portion of the first encoding field.  
     
     
         6 . The method of  claim 1 , further including configuring a memory associated with the processor so that a portion of the memory corresponding to the extended register space is used exclusively by the processor.  
     
     
         7 . The method of  claim 6 , further including storing information from the extended register space within the portion of the memory corresponding to the extended register space in response to a context switch.  
     
     
         8 . The method of  claim 1 , further including associating a portion of a second encoding field of the instruction with a second operand of the instruction.  
     
     
         9 . The method of  claim 8 , wherein associating the portion of the second encoding field with the second operand includes associating a portion of an Mr/m field with one of a source and a destination operand.  
     
     
         10 . The method of  claim 1 , further including associating third and fourth portions of the first encoding field and a portion of a second encoding field of the instruction with second and third operands if the first portion of the first encoding field matches the value associated with the extended register space.  
     
     
         11 . A method of accessing a register space associated with a processor, the method comprising: 
 comparing a first portion of a displacement field of an instruction to a value associated with the register space; and    associating an operand of the instruction with a second portion of the displacement field if the first portion of the displacement field matches the value associated with the register space.    
     
     
         12 . The method of  claim 11 , wherein comparing the first portion of the displacement field to the value associated with the register space includes comparing a tag portion of the displacement field to a tag associated with the register space.  
     
     
         13 . The method of  claim 12 , wherein comparing the tag portion of the displacement field to the tag associated with the register space includes comparing a predetermined number of most significant bits of the displacement field to the tag associated with the register space.  
     
     
         14 . The method of  claim 11 , wherein associating the operand of the instruction with the second portion of the displacement field if the first portion of the displacement field matches the value associated with the register space includes associating one of a source and a destination operand with the second portion of the displacement field.  
     
     
         15 . The method of  claim 11 , further including configuring a system memory so that a portion of the system memory corresponding to the register space is not shared.  
     
     
         16 . The method of  claim 11 , further including associating third and fourth portions of the displacement field and a portion of an Mr/m field with second and third operands if the first portion of the displacement field matches the value associated with the register space.  
     
     
         17 . A method of processing an instruction requiring access to a register space associated with a processor, the method comprising: 
 comparing a tag portion of a first encoding field of the instruction to a value associated with the register space; and    decoding the instruction to associate first and second operands of the instruction with respective first and second registers within the register space.    
     
     
         18 . The method of  claim 17 , wherein comparing the tag portion of the first encoding field of the instruction to the value associated with the register space includes comparing a portion of a displacement field to the value associated with the register space.  
     
     
         19 . The method of  claim 17 , wherein decoding the instruction to associate the first and second operands of the instruction with the respective first and second registers includes associating a register index portion of the first encoding field with the first operand and a portion of a second encoding field of the instruction with the second operand.  
     
     
         20 . The method of  claim 19 , wherein associating the register index portion of the first encoding field with the first operand and the portion of the second encoding field with the second operand includes associating a portion of a displacement field with the first operand and a portion of an Mr/m field with the second operand.  
     
     
         21 . The method of  claim 17 , further including tracking changes within a base register and restarting the instruction in response to detection of a change affecting the instruction.  
     
     
         22 . The method of  claim 17 , further including comparing the tag portion of the first encoding field of the instruction to a plurality of values, each of which is associated with a portion of the register space.  
     
     
         23 . The method of  claim 17 , further including saving the information stored within the register space in response to a context switch.  
     
     
         24 . The method of  claim 17 , further including mapping registers not located within the register space into the register space.  
     
     
         25 . The method of  claim 17 , further including using a microcode trace to store information associated with accessing the register space.  
     
     
         26 . The method of  claim 17 , further including emulating the functionality of the instruction within a fault handler in response to an attempt by the instruction to access an unmapped memory address.  
     
     
         27 . A processor, comprising: 
 a register space;    an instruction decoding pipeline; and    microcode adapted to cause the processor to process an instruction requiring access to the register space within the instruction decoding pipeline so that a first portion of a first encoding field of the instruction is compared to a value associated with the register space and so that a first operand of the instruction is associated with a second portion of the first encoding field if the first portion of the first encoding field matches the value associated with the register space.    
     
     
         28 . The processor of  claim 27 , wherein the register space includes first and second portions and wherein the first portion contains fewer registers than the second portion.  
     
     
         29 . The processor of  claim 27 , wherein the register space is physically integrated within the processor.  
     
     
         30 . The processor of  claim 27 , wherein the instruction decoding pipeline includes a plurality of decoders adapted to perform parallel decoding of the instruction.  
     
     
         31 . The processor of  claim 27 , wherein the first encoding field is a displacement addressing field and wherein the first portion of the first encoding field is one of a memory page identifier and a tag.  
     
     
         32 . The processor of  claim 27 , wherein the second portion of the first encoding field is one of a register index and an offset.  
     
     
         33 . A computer system, comprising: 
 a memory controller;    a system memory coupled to the memory controller; and    a processor having a register space and coupled to the memory controller, wherein the processor is programmed to process an instruction requiring access to the register space so that a first portion of an encoding field of the instruction is compared to a value associated with the register space and so that an operand of the instruction is associated with a second portion of the encoding field if the first portion of the encoding field matches the value associated with the register space.    
     
     
         34 . The computer system of  claim 33 , wherein a portion of the register space portion corresponds to a page of the system memory.  
     
     
         35 . The computer system of  claim 33 , wherein the register space is physically integrated within the processor.  
     
     
         36 . The computer system of  claim 33 , wherein the register space includes first and second portions and wherein the first portion contains fewer registers than the second portion.  
     
     
         37 . A method of processing computer readable instructions, the method comprising: 
 providing a first processor having a first number of registers;    defining a field in an instruction set associated with a second processor having a second number of registers less than the first number of registers so that an instruction from the instruction set that access an off-chip resource when executed by the second processor accesses an on-chip resource when executed by the first processor.    
     
     
         38 . The method of  claim 37 , wherein providing the first processor having the first number of registers includes providing a processor having more than eight general purpose registers.  
     
     
         39 . The method of  claim 37 , wherein defining the field in the instruction set includes defining a tag within a displacement field of the instruction set.  
     
     
         40 . The method of  claim 39 , wherein defining the field in the instruction set associated with the second processor having the second number of registers less than the first number of registers so that the instruction from the instruction set that access the off-chip resource when executed by the second processor accesses the on-chip resource when executed by the first processor includes using a portion of the field to access the on-chip resource.  
     
     
         41 . A method of executing an instruction, comprising: 
 providing a processor with an extended set of on-chip registers;    encoding the instruction with an address of a first register in the extended set of on-chip registers;    executing the instruction using only data from the first register and data from a second on-chip register associated with the processor.    
     
     
         42 . The method of  claim 41 , wherein the second register is in the extended set of registers.  
     
     
         43 . The method of  claim 41 , wherein the second register is in a second set of on-chip registers associated with the processor.  
     
     
         44 . A processor, comprising: 
 a first set of registers;    an extended set of registers;    a decoder to decode an instruction so that the instruction is executed using only data from at least one of the first set and extended set of registers.    
     
     
         45 . The processor of  claim 44 , wherein the decoder comprises: 
 a first decoder to decode an opcode portion of an instruction; and    a second decoder to decode a tag portion of the instruction at substantially the same time the first decoder decodes the opcode portion of the instruction.