Method of forming flash memories with high coupling ratio and the structure of the same

Abstract

The flash memory structure includes a substrate having trenches formed therein, a first dielectric layer and a first conductive layer are stacked on the substrate. Isolations are formed in the trenches and protruding over the surface of the substrate, wherein the first conductive layer is also protruded over the isolations. A second conductive layer is lying the surface of the first conductive layer and a second dielectric layer formed thereon. A third conductive layer is formed on the second dielectric layer. The floating gate is consisted of first conductive layer and the second conductive layer.

What is claimed is:  
     
         1 . A method for manufacturing a nonvolatile memory on a substrate, said method comprising the steps of: 
 forming a tunneling dielectric layer on said substrate;    forming a first conductive layer on said tunneling dielectric layer;    patterning said first polysilicon layer, said tunneling dielectric layer and said substrate to form trenches therein;    forming a gap-filling material into said trenches and over said substrate;    removing a portion of said gap-filling material to form trench isolations and self-aligned first portion of a floating gate adjacent to said trench isolations;    etching a portion of said trench isolations to form slots between said etched first conductive layer;    forming a second conductive layer over a surface of said slots and said etched first conductive layer;    etching said second conductive layer, thereby forming sidewall spacers on said slot;    forming a second dielectric layer on said trench isolation, said sidewall spacers and said first conductive layer; and    forming a third conductive layer on said second dielectric layer to act as a control gate.    
     
     
         2 . The method of  claim 1 , further comprising forming a fourth conductive layer before forming said second conductive layer.  
     
     
         3 . The method of  claim 1 , wherein said tunneling dielectric layer comprises silicon oxide.  
     
     
         4 . The method of  claim 1 , wherein said second dielectric comprises ONO (oxide/nitride/oxide).  
     
     
         5 . The method of  claim 1 , wherein said second dielectric comprises ON (oxide/nitride).  
     
     
         6 . The method of  claim 1 , wherein said first conductive layer, second conductive layer, said third conductive layer are selected from polysilicon, alloy or metal.  
     
     
         7 . A method for manufacturing a nonvolatile memory on a substrate, said method comprising the steps of: 
 forming a tunneling dielectric layer on said substrate;    forming a first conductive layer on said tunneling dielectric layer;    patterning said first polysilicon layer, said tunneling dielectric layer and said substrate to form trenches therein;    forming a gap-filling material into said trenches and over said substrate;    removing a portion of said gap-filling material to form trench isolations and self-aligned first portion of a floating gate adjacent to said trench isolations;    etching a portion of said trench isolations to form slots between said etched first conductive layer;    forming a second dielectric layer on said trench isolation and said first conductive layer; and    forming a second conductive layer on said second dielectric layer to act as a control gate.    
     
     
         8 . The method of  claim 7 , further comprising forming a third conductive layer before forming said second dielectric layer; 
 etching said third conductive layer to form sidewall spacers.    
     
     
         9 . The method of  claim 7 , wherein said tunneling dielectric layer comprises silicon oxide.  
     
     
         10 . The method of  claim 7 , wherein said second dielectric comprises ONO (oxide/nitride/oxide).  
     
     
         11 . The method of  claim 7 , wherein said second dielectric comprises ON (oxide/nitride).  
     
     
         12 . The method of  claim 7 , wherein said first conductive layer and said second conductive layer are selected from polysilicon, alloy or metal.  
     
     
         13 . A nonvolatile memory comprising: 
 a substrate having trenches formed therein;    a first dielectric layer formed on said substrate;    a first conductive layer stacked on said first dielectric layer;    isolations formed in said trenches and protruding over a surface of said substrate, wherein said first conductive layer is also protruded over said isolations;    a second conductive layer formed on a surface of said first conductive layer;    a second dielectric layer formed on said second conductive layer;    a third conductive layer formed n said second dielectric layer as a control gate; and    wherein a floating gate is consisted of said first conductive layer and said second conductive layer.    
     
     
         14 . The nonvolatile memory of  claim 13 , further comprising sidewall spacers on said second conductive layer.  
     
     
         15 . The nonvolatile memory of  claim 13 , wherein said second dielectric comprises ONO (oxide/nitride/oxide) or ON (oxide/nitride).  
     
     
         16 . The nonvolatile memory of  claim 13 , wherein said first conductive layer and said second conductive layer are selected from polysilicon, alloy or metal.  
     
     
         17 . A nonvolatile memory comprising: 
 a substrate having trenches formed therein;    a first dielectric layer formed on said substrate;    a first conductive layer stacked on said first dielectric layer;    isolations formed in said trenches and protruding over a surface of said substrate, wherein said first conductive layer is also protruded over said isolations;    a second dielectric layer formed on said first conductive layer; and    a second conductive layer formed on said second dielectric layer as a control gate.    
     
     
         18 . The nonvolatile memo of  claim 17 , further comprising sidewall spacers on said first conductive layer, wherein a floating gate is consisted of said first conductive layer and said sidewall spacers.  
     
     
         19 . The nonvolatile memory of  claim 17 , wherein said second dielectric comprises ONO (oxide/nitride/oxide) or ON (oxide/nitride).  
     
     
         20 . The nonvolatile memory of  claim 17 , wherein said first conductive layer and said second conductive layer are selected from polysilicon, alloy or metal.