Method for controlling die attach fillet height to reduce die shear stress

Abstract

A method and an apparatus for preventing cracking and delamination in a packaged semiconductor chip by controlling the die attach fillet height. Specifically, the present invention controls the die attach material height, thereby controlling the die attach fillet height, and thereby reducing shear stress in the die itself. Advantages of the present invention include increasing wire-bond reliability and package reliability without the need for requalification of existing products. By using currently qualified molding compounds and die attach epoxies in conjunction with the present technique for controlling the die attach epoxy height in order to control the die attach fillet height, the overall assembly process may be maintained. Thus, neither thermal performance nor electrical performance is compromised.

What is claimed:  
     
         1 . A method of reducing shear stress in a packaged semiconductor chip, comprising the steps of: 
 providing a semiconductor chip package base having a semiconductor chip disposed therein and having a die attachment area;    providing a die having at least one side, 
 said die comprising a semiconductor material selected from a group consisting essentially of silicon (Si), germanium (Ge), and gallium arsenide (GaAs), and  
 each said at least one side having a thickness and a width;  
   providing a die attach material;    controlling an amount of said die attach material disposed between said die and said semiconductor chip package base, 
 whereby at least one portion of said die attach material forms at least one meniscus on said at least one side of the die,  
 whereby said at least one meniscus forms at least one die attach fillet upon curing of said die attach material,  
 thereby controlling at least one height of said at least one die attach fillet, and  
 thereby reducing shear stress in said die; and  
   completing packaging of said semiconductor chip.    
     
     
         2 . A method, as recited in  claim 1 , wherein said die comprises a thickness in a range of approximately 4 mils to approximately 30 mils.  
     
     
         3 . A method, as recited in  claim 1 , wherein said die attach material comprises an epoxy.  
     
     
         4 . A method, as recited in  claim 1 , wherein said at least one die attach fillet comprises a standard height in a range of approximately 0% to approximately 75% of said die thickness.  
     
     
         5 . A method, as recited in  claim 4 , wherein said semiconductor chip package base comprises a ball grid array (BGA).  
     
     
         6 . A method, as recited in  claim 1 , wherein said at least one die attach fillet comprises a standard height in a range of greater than approximately 33% to approximately 75% of said die thickness.  
     
     
         7 . A method, as recited in  claim 6 , wherein said standard height is constrained in said range of greater than approximately 33% to approximately 75% of said die thickness along an approximately central 50% of said die width.  
     
     
         8 . A method, as recited in  claim 1 , wherein said completing step comprises providing a molding compound disposed on said die, on said fillet, on at least one portion of said die attach material, and on at least one portion of said package base.  
     
     
         9 . A method, as recited in  claim 8 , wherein said semiconductor chip package base comprises a ball grid array (BGA).  
     
     
         10 . A method, as recited in  claim 1 , wherein said semiconductor chip package base comprises a ball grid array (BGA).  
     
     
         11 . A reduced shear stress packaged semiconductor chip, comprising: 
 a semiconductor chip package base having a semiconductor chip disposed therein and having a die attachment area;    a die having at least one side, 
 said die comprising a semiconductor material selected from a group consisting essentially of silicon (Si), germanium (Ge), and gallium arsenide (GaAs), and  
 each said at least one side having a thickness and a width; and  
   a controlled amount of die attach material disposed between said die and said semiconductor chip package base; 
 at least one portion of said die attach material forming at least one meniscus on said at least one side of said die,  
 said at least one meniscus forming at least one die attach fillet upon curing of said die attach material,  
 said at least one die attach fillet having at least one controlled height, and  
 said die having reduced shear stress.  
   
     
     
         12 . A packaged semiconductor chip, as recited in  claim 11 , wherein said die comprises a thickness in a range of approximately 4 mils to approximately 30 mils.  
     
     
         13 . A packaged semiconductor chip, as recited in  claim 11 , wherein said die attach material comprises an epoxy.  
     
     
         14 . A packaged semiconductor chip, as recited in  claim 11 , wherein said at least one die attach fillet comprises a standard height in a range of approximately 0% to approximately 75% of said die thickness.  
     
     
         15 . A packaged semiconductor chip, as recited in  claim 14 , wherein said semiconductor chip package base comprises a ball grid array (BGA).  
     
     
         16 . A packaged semiconductor chip, as recited in  claim 11 , wherein said at least one die attach fillet comprises a standard height in a range of greater than approximately 33% to approximately 75% of said die thickness.  
     
     
         17 . A packaged semiconductor chip, as recited in  claim 16 , wherein said standard height is constrained in said range of greater than approximately 33% to approximately 75% of said die thickness along an approximately central 50% of said die width.  
     
     
         18 . A packaged semiconductor chip, as recited in  claim 11 , further comprising a molding compound disposed on said die, on said fillet, on at least one portion of said die attach material, and on at least one portion of said package base.  
     
     
         19 . A packaged semiconductor chip, as recited in  claim 18 , wherein said semiconductor chip package base comprises a ball grid array (BGA).  
     
     
         20 . A packaged semiconductor chip, as recited in  claim 11 , wherein said semiconductor chip package base comprises a ball grid array (BGA).