US2004046243A1PendingUtilityA1
Methods of split cavity wall plating for an integrated circuit package
Priority: Sep 15, 1998Filed: Sep 8, 2003Published: Mar 11, 2004
Est. expirySep 15, 2018(expired)· nominal 20-yr term from priority
H10W 74/00H10W 72/07554H10W 72/951H10W 72/932H10W 72/551H10W 72/547H10W 72/075H10W 70/655H10W 74/114H10W 76/157Y10T29/49155Y10T29/4913Y10T29/49126Y10T29/49131
33
PatentIndex Score
0
Cited by
0
References
0
Claims
Abstract
An electronic package that may include a first bond pad and a second bond pad located on a bond shelf. The bond shelf may have an edge. The package may have a first conductive bus that may be connected to the first bond pad by a first conductive strip that extends along the edge of the bond shelf. The package may also have a second conductive bus that may be connected to the second bond pad by a second conductive strip that extends along the edge of the bond shelf.
Claims
exact text as granted — not AI-modifiedWhat is claimed is:
1 - 16 . (Cancelled)
17 . (New) A method of forming an integrated circuit package, comprising:
providing a package housing having a first plurality of bonding pads located on a first bond shelf, the first bond shelf having a first edge; forming a first conductive strip along the first edge of the first bond shelf, the first conductive strip wrapping around the edge of the first bond shelf from at least one of the first plurality of bonding pads on the first bond shelf to a first conductor under the first bond shelf; and, removing a portion of the first conductive strip.
18 . (New) The method as recited in claim 17 , wherein
the first conductive strip is formed by plating a conductive material onto the first edge.
19 . (New) The method as recited in claim 17 , wherein
the first conductor under the first bond shelf is a power bus.
20 . (New) The method as recited in claim 17 , wherein
the first conductor under the first bond shelf is a routing trace.
21 . (New) The method as recited in claim 17 , wherein
the portion of the first conductive strip is removed by
drilling a portion of the first bond shelf.
22 . (New) The method as recited in claim 21 , wherein
the portion drilled in the first bond shelf is a notch.
23 . (New) The method as recited in claim 17 , wherein
the portion of the first conductive strip is removed by
etching away a portion of the first conductive strip of the first bond shelf.
24 . (New) The method as recited in claim 17 , wherein
the package housing is provided by
forming a first conductive layer on a first dielectric substrate,
placing a second dielectric substrate on the first conductive layer of the first dielectric substrate, the second dielectric substrate having a second conductive layer, and
etching the second conductive layer to form the first plurality of bonding pads.
25 . (New) The method as recited in claim 24 , wherein
the first conductive layer forms the first conductor under the first bond shelf.
26 . (New) The method as recited in claim 24 , wherein
the etching of the second conductive layer to further form a second conductor, and the package housing has a second plurality of bonding pads located on a second bond shelf, the second bond shelf having a second edge, the package housing is further provided by
placing a third dielectric substrate on the second conductive layer of the second dielectric substrate, the third dielectric substrate having a third conductive layer, and
etching the third conductive layer to form a second plurality of bonding pads, and
the method further includes
forming a second conductive strip along the second edge of the second bond shelf, the second conductive strip wrapping around the second edge of the second bond shelf from at least one of the second plurality of bonding pads on the second bond shelf to the second conductor under the second bond shelf.
27 . (New) The method as recited in claim 26 , wherein
the second conductive layer forms the second conductor under the second bond shelf.
28 . (New) The method as recited in claim 26 , wherein
the second conductive strip is formed by plating a conductive material onto the second edge.
29 . (New) The method as recited in claim 26 , wherein
the second conductor under the second bond shelf is a power bus.
30 . (New) The method as recited in claim 26 , wherein
the second conductor under the second bond shelf is a routing trace.
31 . (New) A method of forming an integrated circuit package, comprising:
providing a package housing having a first bond shelf with a top surface and an inside surface; forming a conductive material along the inside surface of the first bond shelf, a first portion of the conductive material wrapping around from the inside surface onto the top surface of the first bond shelf to form at least one of a first plurality of bonding pads on the top surface of the first bond shelf; and, removing a second portion of the conductive material along the inside surface of the bond shelf to form a pair of separate conductive strips along the inside surface of the bond shelf.
32 . (New) The method as recited in claim 31 , wherein
the conductive material is formed along the inside surface by plating a conductive material onto the inside surface.
33 . (New) The method as recited in claim 31 , wherein
the second portion of the conductive material is removed by
drilling a portion of the first bond shelf.
34 . (New) The method as recited in claim 33 , wherein
the portion drilled in the first bond shelf is a notch.
35 . (New) The method as recited in claim 31 , wherein
the second portion of the conductive material is removed by etching away a portion of the conductive material from the inside surface of the first bond shelf.
36 . (New) A method of forming an integrated circuit package, comprising:
providing a package housing having a rectangular bond shelf with a rectangular top surface and an inside surface perpendicular with the top surface, the bond shelf having a first plurality of bonding pads located on the top surface; forming a conductive material along the side surface of the bond shelf, a first portion of the conductive material wrapping around from the inside surface onto the top surface of the bond shelf to couple to at least one of the first plurality of bonding pads on the top surface of the bond shelf; and, removing a second portion of the conductive material along the inside surface of the bond shelf to form a pair of separate conductive strips along the inside surface of the bond shelf.
37 . (New) The method as recited in claim 36 , wherein
the conductive material is formed along the inside surface by plating a conductive material onto the inside surface of the bond shelf.
38 . (New) The method as recited in claim 36 , wherein
the second portion of the conductive material is removed by
drilling a portion of the bond shelf.
39 . (New) The method as recited in claim 38 , wherein
the portion drilled in the bond shelf is a notch.
40 . (New) The method as recited in claim 36 , wherein
the second portion of the conductive material is removed by etching away a portion of the conductive material from the inside of the first bond shelf.Join the waitlist — get patent alerts
Track US2004046243A1 — get alerts on status changes and closely related new filings.
We store only your email — no account needed. See our privacy policy.