Thin film transistor including polycrystalline active layer and method for fabricating the same

Abstract

A thin film transistor (TFT) including a polycrystalline active layer and a method for making the same are disclosed. An amorphous silicon layer is deposited on a substrate and is crystallized by using MILC (metal induced lateral crystallization) to provide a poly-silicon active layer of the TFT. Specifically, the amorphous silicon layer is poly-crystallized during a thermal treatment of the active layer. The thermal treatment causes the MILC of the active layer propagating from portions of the source and the drain regions on which MILC source metal is formed through the contact holes of the TFT.

What is claimed is:  
     
         1 . A thin film transistor (TFT) comprising: 
 a substrate; a polysilicon active layer formed on the substrate and providing a source, a drain and a channel regions of the TFT; a gate insulation layer and a gate electrode formed on said substrate and said active layer; a contact insulation layer covering said substrate, said active layer and said gate electrode and including contact holes formed to expose portions of said source and said drain regions; and contact electrodes electrically connected to said source and drain regions through said contact holes,    wherein said active layer of the TFT is formed by crystallizing an amorphous silicon layer fmmed on said substrate by conducting a thelmal treatment of the amorphous silicon layer, and the thermal treatment causes a MILC (metal induced lateral crystallization) propagating from the portions of said source and drain regions exposed by said contact holes and having MILC source metal formed thereon.    
     
     
         2 . The thin film transistor according to  claim 1 , wherein the MILC source metal contains at least one ofNi, Pd, Ti, Ag, Au, Al, Sn, Sb, Cu, Co, Cr, Mo, Tr, Ru, Rh, Cd and Pt.  
     
     
         3 . The thin film transistor according to  claim 1 , wherein the MILC source metal is formed with a thickness in the range of 1 Å to 200 Å by sputtering, heating evaporation or CVD.  
     
     
         4 . The thin film transistor according to  claim 1 , wherein the thermal treatment is conducted at a temperature range of 400 DC to 600 DC for 0.1 to 50 hours.  
     
     
         5 . The thin film transistor according to  claim 1 , wherein said contact electrode is made of the same material as the MILC source metal.  
     
     
         6 . The thin film transistor according to  claim 5 , wherein said contact electrode and said MILC source metal are formed as a single body.  
     
     
         7 . The thin film transistor according to  claim 6 , wherein the MILC source metal integrated with said contact electrode has a thickness in the range of 500 Å to 10,000 Å.  
     
     
         8 . The thin film transistor according to  claim 1 , further comprising a buffer layer formed between said substrate and said active layer.  
     
     
         9 . The thin film transistor according to  claim 1 , wherein said active layer includes a lightly doped drain (LDD) region or an offset junction region.  
     
     
         10 . The thin film transistor according to  claim 1 , wherein said active layer is formed by an impurity doping using said gate electrode as a mask using ion implantation method or ion shower doping method.  
     
     
         11 . The thin film transistor according to  claim 1 , wherein said contact holes are formed at asymmetric locations with respect to said gate electrode, and accordingly said MILC source metal is formed at asymmetric locations with respect to said channel region.  
     
     
         12 . The thin film transistor according to  claim 1 , wherein the locations of said MILC source metal are determined so that a boundary between the MILC crystallization regions is formed outside of said channel region, when each of MILC crystallization regions grows from the portions of said source and drain regions on which said MILC source metal is formed during the thermal treatment of said active layer.  
     
     
         13 . The thin film transistor according to  claim 1 , which is characterized by comprising at least two gate electrodes.  
     
     
         14 . The thin film transistor (TFT) according to  claim 13 , wherein the locations of said contact holes are determined so that a boundary between the MILC crystallization regions is formed between said gate electrodes, when each of the MILC crystallization regions grows from the portions of said source and drain regions on which said MILC source metal is formed during the thermal treatment of said active layer.  
     
     
         15 . The thin film transistor (TFT) according to  claim 10 , wherein the crystallization of said active layer by the MILC and the activation of the doped impurity are simultaneously achieved during the thermal treatment of said active layer.