US2004042328A1PendingUtilityA1

Magnetic material, memory and information reproducing method of the same

Assignee: CANON KKPriority: Mar 13, 2001Filed: Sep 2, 2003Published: Mar 4, 2004
Est. expiryMar 13, 2021(expired)· nominal 20-yr term from priority
Inventors:Tadahiko Hirai
G11C 11/15
34
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Claims

Abstract

To provide an MRAM, in which the information readout speed of the MRAM is increased up to a speed comparable to a synchronous DRAM, the MRAM includes a plurality of units each including a plurality of memory elements arranged in a matrix form, each of which includes a non-magnetic layer sandwiched between a hard layer made of a magnetic material and a soft layer made of a magnetic substance having coercive force lower than the hard layer; a plurality of bit lines arranged in parallel with each other; and a plurality of sense amplifiers connected to the respective bit lines, wherein the plurality of sense amplifiers in the same unit are activated at the same time to read out information in the unit, the units are successively changed over in synchronization with a clock pulse, and the sense amplifiers in the different units are successively activated so that information in the plurality of units is parallel outputted in synchronization with the clock pulse, and information of each of the units is continuously reproduced.

Claims

exact text as granted — not AI-modified
What is claimed is:  
     
         1 . An MRAM comprising a plurality of units each including: 
 a plurality of memory elements each of which includes a non-magnetic layer between a hard layer consists of a magnetic material and a soft layer consists of a magnetic material having coercive force lower than the hard layer;    a plurality of bit lines arranged in parallel with each other; and    a plurality of sense amplifiers connected to the respective bit lines,    wherein the plurality of sense amplifiers in the same unit are activated at the same line to read out information in the unit, the units are successively changed over in synchronization with a clock pulse, and the sense amplifiers in the different units are successively activated, so that information in the plurality of units is parallel outputted in synchronization with the clock pulse, and information of each of the units is continuously reproduced.    
     
     
         2 . An MRAM according to  claim 1 , further comprising a plurality of switching elements for selecting the memory elements, and word lines intersecting with the bit lines, disposed for every column, and connected to control electrodes of the switching elements, wherein a pulse is applied to the word line connected to the plurality of switching elements for selecting the plurality of memory elements disposed in the same column, so that information is outputted in parallel for every column in the unit.  
     
     
         3 . An MRAM according to  claim 1 , wherein after an electric resistance value of the memory element is detected and beld, an electric resistance value after a magnetization direction of the soft layer is inverted by applying a magnetic field is detected, and the electric resistance values before and after the magnetization direction is inverted are inputted to the sense amplifier to reproduce information.  
     
     
         4 . An MRAM according to  claim 1 , wherein the unit includes a circuit for inputting a predetermined reference value as a voltage signal to one terminal of the sense amplifier.  
     
     
         5 . An MRAM according to  claim 1 , wherein the number of the sense amplifiers activated at the same time in each of the units is equal to the number of bits of the information parallel outputted per clock pulse.  
     
     
         6 . An MRAM according to  claim 1 , wherein the memory element is a tunnel magneto-resistance element.  
     
     
         7 . An MRAM according to  claim 1 , wherein a magnetization direction of the magnetic film of the memory element is vertical to a film plane.  
     
     
         8 . An MRAM according to  claim 1 , wherein said plurality of memory elements are arranged in a matrix form.

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