Transistor device

Abstract

To attain a comparatively high breakdown voltage at a high avalanche strength and with the physical size simultaneously being as small as possible, the invention proposes constructing a transistor device in a semiconductor material region in which a first source/drain region is used as a source region and in which the source region has a comparatively reduced surface charge or surface charge density.

We claim:  
     
         1 . A transistor device, comprising: 
 a semiconductor material region having a first source/drain region, a second source/drain region, a gate region and a body region located between said first source/drain region and said second source/drain region, said first source/drain region serving as a source region having a comparatively reduced charge, charge density, surface charge, or surface charge density; and    a parasitic bipolar transistor having an emitter, a collector, and a base;    said first source/drain region forming said emitter of said parasitic bipolar transistor, said second source/drain region forming said collector of said parasitic bipolar transistor, and said body region forming said base of said parasitic bipolar transistor;    said parasitic bipolar transistor having a sufficiently low current gain factor; and    the transistor device having an essentially unreduced breakdown voltage.    
     
     
         2 . The transistor device according to  claim 1 , wherein said first source/drain region is formed from a semiconductor material with a bandgap that is lower than said body region.  
     
     
         3 . The transistor device according to  claim 2 , wherein said bandgap that is 100 meV lower than with silicon.  
     
     
         4 . The transistor device according to  claim 1 , wherein said first source/drain region includes a semiconductor material having a lower bandgap than said body region.  
     
     
         5 . The transistor device according to  claim 4 , wherein said bandgap that is 100 meV lower than with silicon.  
     
     
         6 . The transistor device according to  claim 1 , wherein: 
 said body region is not electrically connected or is only poorly electrically connected to said first source/drain region; and    said body region is not connected or is only poorly connected to an applied source potential during operation.    
     
     
         7 . The transistor device according to  claim 1 , wherein said first source/drain region has a surface charge density that is reduced from a range of approximately 10 14  cm −2  to 10 16  cm −2  to a range of approximately 10 9  cm −2  to 10 13  cm −2 .  
     
     
         8 . The transistor device according to  claim 1 , wherein said first source/drain region and said body region have a comparatively high contact resistance therebetween.  
     
     
         9 . The transistor device according to  claim 1 , further comprising: 
 a connecting region for said first source/drain region;    said connecting region and said body region having a comparatively high contact resistance therebetween.    
     
     
         10 . The transistor device according to  claim 1 , further comprising: 
 a connecting region for said first source/drain region;    said first source/drain region having material; and    only said material of said first source/drain region being between said connecting region of said first source/drain region and said body region such that at most indirect electrical contact is produced between said body region and said connecting region of said first source/drain region and such that there is no common connecting metallization.    
     
     
         11 . The transistor device according to  claim 1 , wherein the transistor device is a field-effect transistor device, a power transistor device, a PMOS transistor device, a planar transistor device and/or a trench transistor device.  
     
     
         12 . The transistor device according to  claim 1 , wherein: 
 the transistor device is a DMOS transistor device;    said source region has a connecting region;    said body region is not connected to said source region or to said connecting region of said source region; and    said charge in said first source/drain region is reduced to such an extent that, as a result, a breakdown voltage is reduced by at most 15% as compared with a breakdown voltage in a case when there is contact between said body region and said source region or between said body region and said connecting region of said source region.    
     
     
         13 . The transistor device according to  claim 1 , wherein: 
 the transistor device is a DMOS transistor device;    said source region has a connecting region;    said body region is not connected to said source region or to said connecting region of said source region; and    said charge in said first source/drain region is reduced to such an extent that, as a result, a breakdown voltage for small currents is reduced by at most 15% as compared with a breakdown voltage in a case when there is contact between said body region and said source region or between said body region and said connecting region of said source region.    
     
     
         14 . The transistor device according to  claim 1 , wherein: 
 the transistor device is a trench DMOS transistor device;    said source region has a connecting region;    said body region is not connected to said source region or to said connecting region of said source region; and    said charge in said first source/drain region is reduced to such an extent that a breakdown voltage is reduced by at most 15% as compared with a breakdown voltage when said body region is in contact with said source region or with said connecting region of said source region.    
     
     
         15 . The transistor device according to  claim 1 , wherein: 
 the transistor device is a trench DMOS transistor device;    said body region is made of a semiconductor material;    said source region is made of a semiconductor material that has a smaller bandgap than said semiconductor material of said body region;    said body region is made of silicon; and    said source region is made of Si 1-x Ge x , semiconductor material with a low bandgap, amorphous semiconductor, amorphous silicon, or amorphous metal.    
     
     
         16 . The transistor device according to  claim 15 , wherein: 
 said source region has a connecting region; and    said surface charge of said source region is reduced such that, as a result, a breakdown voltage for small currents is reduced by at most 15% as compared with a breakdown voltage when there is contact between said body region and said source region or said connecting region of said source region.    
     
     
         17 . The transistor device according to  claim 1 , wherein: 
 the transistor device is a trench DMOS transistor device;    said source region has a connecting region;    said body region is not connected to said source region or to said connecting region of said source region;    said body region is formed from a said semiconductor material; and    said source region is formed from a semiconductor material that has a smaller bandgap than said semiconductor material of said body region.    
     
     
         18 . The transistor device according to  claim 1 , wherein: 
 said body region is made of silicon; and    said source region is made of Si 1-x Ge x , semiconductor material with a low bandgap, amorphous semiconductor, amorphous silicon, or amorphous metal.    
     
     
         19 . The transistor device according to  claim 1 , wherein: 
 the transistor device is a trench DMOS transistor device;    said source region has a connecting region;    said body region is not connected to said source region or to said connecting region of said source region;    said body region is made of a semiconductor material having a conduction band edge; and    said source region is made of a semiconductor material having a conduction band edge with a lower energy level than said conduction band edge of said semiconductor material of said body region if said conduction band edge of said source region and said conduction band edge of said body region are compared with one another in an undoped case or state.    
     
     
         20 . The transistor device according to  claim 1 , wherein: 
 the transistor device is a trench DMOS transistor device;    said source region has a connecting region;    said body region is not connected to said source region or to said connecting region of said source region;    said body region is made of a semiconductor material having a valency band edge; and    said source region is made of a semiconductor material having a valency band edge with a higher energy level than said valency band edge of said semiconductor material of said body region if said valency band edge of said source region and said valency band edge of said body region are compared with one another in an undoped case or state.    
     
     
         21 . The transistor device according to  claim 1 , wherein: 
 the transistor device is a trench DMOS transistor device;    said source region has a connecting region;    said body region is not connected to said source region or to said connecting region of said source region; and    said charge of said source region is reduced to such an extent that a breakdown voltage for small currents is reduced only a little as compared with a breakdown voltage when said body region is connected to said source region or to said connecting region of said source region.    
     
     
         22 . The transistor device according to  claim 21 , wherein contact is made with said source region by providing a dopant that allows good contact; and said dopant has a charge that is not electrically active in an off case.  
     
     
         23 . The transistor device according to  claim 21 , wherein said dopant is selenium.  
     
     
         24 . The transistor device according to  claim 1 , further comprising: 
 an amorphous or polycrystalline undoped, weakly doped or highly doped semiconductor layer configured on said source region for making contact with said source region;    said source region being approximately 10 nm thick.    
     
     
         25 . The transistor device according to  claim 1 , further comprising: 
 an amorphous or polycrystalline highly doped semiconductor layer configured on said source region for making contact with said source region; and    a metallization provided for said highly doped semiconductor layer;    said source region being approximately 10 nm thick; and    said highly doped semiconductor layer having a doping of between approximately 10 19  cm −2  and approximately 10 20  cm −3 .    
     
     
         26 . The transistor device according to  claim 1 , wherein: 
 the transistor device is a DMOS transistor device; and    said source region is in an epitaxially deposited form.    
     
     
         27 . The transistor device according to  claim 26 , wherein: 
 said source region has semiconductor material with a relatively small bandgap; and    said semiconductor material of said source region has a conduction band edge with a relatively low energy level or a valency band edge with a relatively high level.    
     
     
         28 . The transistor device according to  claim 26 , wherein said charge, said charge density, said surface charge, or said surface charge density of said source region is below 10 14  cm −2 .