US2004040855A1PendingUtilityA1

Method for low-cost redistribution and under-bump metallization for flip-chip and wafer-level BGA silicon device packages

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Priority: Aug 28, 2002Filed: Aug 28, 2002Published: Mar 4, 2004
Est. expiryAug 28, 2022(expired)· nominal 20-yr term from priority
Inventors:Victor Batinovich
C25D 7/123H10P 14/47H10W 72/952H10W 72/923H10W 72/251H10W 72/29H10W 70/05H10W 74/129H10W 72/012H10W 72/942H10W 72/9223H10W 72/244H10W 72/019H10W 72/20
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Claims

Abstract

A method for redistributing bond pad locations on an IC die incorporates steps of (a) depositing a dielectric layer over the IC die and opening vias through the dielectric layer to the bond pads; (b) depositing a thin seed layer of electrically conductive material over the dielectric layer and exposed bond pads, and patterning the seed layer to provide redistribution lines from individual ones of the bond pads to new locations for the bond pads; and (c) increasing the thickness of the redistribution lines by electroplating a conductive material onto the seed layer material. In some cases multiple relocations are made in the distribution.

Claims

exact text as granted — not AI-modified
What is claimed is:  
     
         1 . A method for redistributing bond pad locations on an IC die, comprising the steps of: 
 (a) depositing a dielectric layer over the IC die and opening vias through the dielectric layer to the bond pads;    (b) depositing a thin seed layer of electrically conductive material over the dielectric layer and exposed bond pads, and patterning the seed layer to provide redistribution lines from individual ones of the bond pads to new locations for the bond pads; and    (c) increasing the thickness of the redistribution lines by electroplating a conductive material onto the seed layer material.    
     
     
         2 . The method of  claim 1  wherein the seed layer is no more than 2000 Angstrom units in thickness.  
     
     
         3 . The method of  claim 1  further comprising a step for providing solder bumps at the new bond pad locations.  
     
     
         4 . The method of  claim 1  wherein the seed layer conductive material is copper or a copper alloy.  
     
     
         5 . The method of  claim 1  wherein the electroplating step plates copper or a copper alloy onto the seed layer.  
     
     
         6 . The method of  claim 3  further comprising a step for applying an under-bump metallization by plating technique before the step for solder bumping.  
     
     
         7 . The method of  claim 1  wherein, in step (a), the dielectric layer is one of silicon oxide or polyamide material.  
     
     
         8 . The method of  claim 1  wherein, in step (b), the seed layer is deposited by sputtering technique.  
     
     
         9 . The method of  claim 3  wherein, in step (b), the seed layer is deposited by an electroless plating technique.  
     
     
         10 . A method for redistributing bond pad locations on an IC die, comprising the steps of: 
 (a) depositing a first dielectric layer over the IC die and opening vias through the first dielectric layer to the bond pads;    (b) depositing a first layer of electrically conductive material over the dielectric layer and exposed bond pads, and patterning the first layer to provide redistribution lines from individual ones of the bond pads to first redistributed locations for the bond pads;    (c) depositing a second dielectric layer over the first redistribution lines and opening vias through the second dielectric layer to the intermediate locations; and    (d) depositing a second layer of electrically-conductive material over the second dielectric layer and exposed intermediate locations, and patterning the second layer to provide redistribution lines from individual ones of the intermediate locations to second redistributed locations.    
     
     
         11 . The method of  claim 10  comprising steps for more than two intermediate locations of the bond pads.  
     
     
         12 . The method of  claim 10  wherein one or both of the first and second electrically-conductive layers is provided by applying a thin seed layer and then increasing the thickness of the electrically-conductive layer by plating technique.  
     
     
         13 . The method of  claim 12  wherein the seed layer is no more than 2000 Angstrom units in thickness.  
     
     
         14 . The method of  claim 10  further comprising a step for providing solder bumps at the second redistributed locations.  
     
     
         15 . The method of  claim 10  wherein the seed layer conductive material is copper or a copper alloy.  
     
     
         16 . The method of  claim 12  wherein the electroplating step plates copper or a copper alloy onto the seed layer.  
     
     
         17 . The method of  claim 14  further comprising a step for applying an under-bump metallization by plating technique before the step for solder bumping.  
     
     
         18 . The method of  claim 10  wherein, in step (a), the dielectric layer is one of silicon oxide or polyamide material.  
     
     
         19 . The method of  claim 12  wherein the seed layer is deposited by sputtering technique.  
     
     
         20 . The method of  claim 12  wherein the seed layer is deposited by an electroless plating technique.

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