Data transfer control method, and peripheral circuit, data processor and data processing system for the method

Abstract

A memory 1 performs its internal operation in response to access requests ( 200, 201 and 202 ) of a CPU 2 in synchronism with the oscillated output of a self-excited oscillator 102 incorporated therein and according to said access requests, and outputs a response request 103 for said access requests to said CPU in synchronism with its internal operation. The CPU performs the access requests for the memory, and fetches data from the outside or outputs the data to the outside in response to and in synchronism with the response request 103 from the accessed memory and according to the kinds of said access requests.

What is claimed is:  
     
         1 . A method of controlling a data transfer between a data processor and its peripheral circuit, comprising the staps of: 
 sending an access request to a peripheral circuit from said data processor;    allowing said peripheral circuit to perform an internal operation according to the access request in synchronism with the output from a self-excited oscillator incorporated therein and in a manner to understand the content of said access request;    sending a response request to said peripheral circuit from said data processor in synchronism with its internal operation in response to said access request; and    transferring data to or from said data processor depending on the type of said access request in synchronism with said response request.    
     
     
         2 . A data transfer controlling method according to  claim 1 , 
 wherein said access request contains the information indicating both the peripheral circuit selected as an object to be accessed and the transfer direction of the data, and    wherein said response request is a signal varying in synchronism with the internal operation of said peripheral circuit.    
     
     
         3 . A peripheral circuit comprising: 
 a cycle timing generator for producing an access cycle signal of an internal operation in response to an access request from a data processor and on the basis of an output of a self-excited oscillator;    an external terminal for outputting said access cycle signal as a response request in response to said access request; and    an internal timing generator for producing an internal operation timing signal in synchronism with said access cycle signal.    
     
     
         4 . A peripheral circuit according to  claim 3 , 
 wherein said peripheral circuit is constructed as a memory including:    a memory cell array having a plurality of memory cells arranged in a matrix form;    a selector for selecting the memory cells on the basis of an external address signal;    a read circuit for reading the data from the selected memory cell; and    a counter for counting the number of continuous data words read from said memory cell array on the basis of a change in said access cycle signal, to stop the oscillation of said self-excited oscillator when the counted result reaches a predetermined count value.    
     
     
         5 . A peripheral circuit according to  claim 4 , 
 wherein said counter has a parameter register for latching said predetermined count value presettably from the outside.    
     
     
         6 . A data processor comprising: 
 an access control circuit for sending an access request to a peripheral circuit;    an input terminal for receiving a response request from the peripheral circuit in response to said access request;    a buffer memory capable of writing/reading on the basis of said response request and in synchronism with an internal operation clock; and    an arithmetic circuit and an input/output buffer circuit connected with said buffer memory.    
     
     
         7 . A data processor according to  claim 6 , further comprising: 
 a central processing unit for controlling said access control circuit, said buffer memory, said arithmetic circuit and said input/output buffer circuit.    
     
     
         8 . A data processor according to  claim 7 , 
 wherein said buffer memory includes a counter for detecting the number of continuous read access requests to said peripheral circuit from said access control circuit, in terms of the number of changes in said response request, whereby said central processing unit receives said detection result as the information meaning the complete of the data acquisition by said access request.    
     
     
         9 . A data processor comprising: 
 an access control circuit for sending an access request to a peripheral circuit;    an input terminal for receiving a response request from the peripheral circuit in response to said access request;    a buffer memory having an asynchronous port for writing/reading on the basis of said response request, and a synchronous port for writing/reading in synchronism with an internal operation clock;    an arithmetic circuit connected with the synchronous port of said buffer memory; and    an input/output buffer circuit connected with the asynchronous port of said buffer memory for interfacing with external devices.    
     
     
         10 . A data processor according to  claim 9 , further comprising: 
 a central processing unit for controlling said access control circuit, said buffer memory, said arithmetic circuit and said input/output buffer circuit.    
     
     
         11 . A data processor according to  claim 10 , 
 wherein said buffer memory includes a counter for detecting the number of continuous read access requests sent to said peripheral circuit from said access control circuit, in terms of the number of changes in said response request, whereby said central processing unit receives said detection result as the information meaning the complete of the data acquisition by said access request.    
     
     
         12 . A data processing system comprising: 
 a peripheral circuit that performs an internal operation according to an access rquest from a data processor and in synchronism with the output of a self-excited oscillator incorporated therein, and outputs a response request to said data processor in synchronism with said internal operation in response to said access request;    a data processor that sends an access request to a desired peripheral circuit and receives a response request from the desired peripheral circuit, thereby transferring data to or from the peripheral circuit depending on the type of said access request; and    a bus connecting said data processor and said peripheral circuit.    
     
     
         13 . A data processing system according to  claim 12 , 
 wherein a plurality of peripheral circuits of different kinds are commonly connected with said bus such that their output terminals for response requests share the single input terminal for response requests of said data processor.