Semiconductor fuses, semiconductor devices containing the same, and methods of making and using the same

Abstract

A fuse for use in a semiconductor device includes spaced-apart terminals with at least two layers of conductive material and a single-layer conductive link joining the spaced-apart terminals and including a single layer of conductive material. A first, lower layer of the terminals of each fuse may be formed from conductively doped polysilicon. The second, upper layer of each fuse terminal may be formed from a polycide, a metal silicide, a metal, or a conductive alloy. The conductive link of each fuse may be formed from either the material of the first layer or the material of the second layer. Methods for fabricating the fuse include forming the first and second layers and patterning the first and second layers so as to form a fuse with the desired structure.

What is claimed is:  
     
         1 . A method for fabricating a fuse on a semiconductor device structure, comprising: 
 forming a conductive layer comprising polysilicon over at least a field isolation region of the semiconductor device structure;    forming another conductive layer over said conductive layer; and    patterning said conductive layer and said another conductive layer to form the fuse, the fuse including spaced-apart terminals and a conductive link joining said spaced-apart terminals, said spaced-apart terminals being formed by said conductive layer and said another conductive layer, said conductive link being formed by only one of said conductive layer and said another conductive layer.    
     
     
         2 . The method of  claim 1 , wherein said forming said another conductive layer comprises forming said another conductive layer to comprise at least one of a metal silicide, a polycide, and a metal.  
     
     
         3 . The method of  claim 1 , wherein said forming said another conductive layer comprises forming said another conductive layer from tungsten.  
     
     
         4 . The method of  claim 1 , wherein said forming said another conductive layer comprises forming a metal silicide layer.  
     
     
         5 . The method of  claim 4 , wherein said forming said metal silicide layer comprises forming one of a tungsten silicide layer, a titanium silicide layer, and a cobalt suicide layer.  
     
     
         6 . The method of  claim 4 , wherein said forming said metal silicide layer comprises depositing metal silicide onto said conductive layer.  
     
     
         7 . The method of  claim 4 , wherein said forming said metal silicide layer comprises: 
 depositing metal onto said conductive layer; and    annealing said metal to at least said polysilicon of said conductive layer.    
     
     
         8 . The method of  claim 7 , wherein said annealing comprises reacting said metal with said polysilicon to form said metal suicide.  
     
     
         9 . The method of  claim 1 , wherein said patterning also comprises patterning at least a portion of a transistor gate conductor.  
     
     
         10 . The method of  claim 1 , wherein said patterning said conductive layer precedes said forming another conductive layer.  
     
     
         11 . The method of  claim 10 , wherein said patterning said conductive layer comprises forming portions of said spaced-apart terminals and said conductive link from said conductive layer.  
     
     
         12 . The method of  claim 1 , wherein said patterning said another conductive layer precedes said patterning said conductive layer.  
     
     
         13 . The method of  claim 1 , wherein said patterning said another conductive layer comprises removing material of said another conductive layer with selectivity over said polysilicon of said conductive layer.  
     
     
         14 . The method of  claim 1 , wherein said patterning said conductive layer and said another conductive layer comprises forming said conductive link to be less massive than said spaced-apart terminals.  
     
     
         15 . The method of  claim 14 , wherein at least one of said patterning said conductive layer and said patterning said another conductive layer comprises forming said conductive link to have a smaller cross-sectional area taken transverse to a length of the fuse than a cross-sectional area of each of said spaced-apart terminals taken transverse to the length of the fuse.  
     
     
         16 . The method of  claim 14 , wherein forming said conductive link is effected substantially simultaneously with said patterning said conductive layer.  
     
     
         17 . A fuse for a semiconductor device structure, comprising: 
 a first layer comprising a first conductive material;    a second layer comprising a second conductive material, said second layer being at least partially superimposed over and in contact with said first layer, said first and second layers forming spaced-apart terminals of the fuse, one of said first and second layers forming a conductive link of the fuse, said conductive link joining at least two terminals of said spaced-apart terminals.    
     
     
         18 . The fuse of  claim 17 , wherein said first conductive material comprises conductively doped polysilicon.  
     
     
         19 . The fuse of  claim 18 , wherein said first conductive material further comprises one of an N-type conductivity dopant and a P-type conductivity dopant.  
     
     
         20 . The fuse of  claim 17 , wherein said second conductive material comprises at least one of a metal silicide, a polycide, and a metal.  
     
     
         21 . The fuse of  claim 20 , wherein said second conductive material comprises a metal silicide.  
     
     
         22 . The fuse of  claim 17 , wherein said second conductive material comprises tungsten or tungsten silicide.  
     
     
         23 . The fuse of  claim 17 , wherein said second conductive material is selectively etchable with respect to said first conductive material.  
     
     
         24 . The fuse of  claim 23 , wherein said first conductive material comprises conductive polysilicon and said second conductive material comprises a metal silicide.  
     
     
         25 . The fuse of  claim 17 , wherein said conductive link has a smaller volume of conductive material than either of said at least two terminals.  
     
     
         26 . The fuse of  claim 17 , wherein said conductive link has a smaller cross-sectional area taken transverse to a length of the fuse than a cross-sectional area of each of said spaced-apart terminals taken transverse to the length of the fuse.  
     
     
         27 . A fuse for use in a semiconductor device structure, comprising: 
 a central region including a single layer comprising conductive material; and    two terminals spaced apart from one another, each of said two terminals in contact with said central region and including a first layer comprising a first conductive material and a second layer comprising a second conductive material, said first layer being continuous and substantially coplanar with said central region.    
     
     
         28 . The fuse of  claim 27 , wherein said conductive material of said single layer of said central region comprises said first conductive material.  
     
     
         29 . The fuse of  claim 27 , wherein said first conductive material comprises conductively doped polysilicon.  
     
     
         30 . The fuse of  claim 29 , wherein said second conductive material comprises at least one of a metal silicide, a polycide, and a metal.  
     
     
         31 . The fuse of  claim 29 , wherein said second conductive material comprises tungsten or tungsten silicide.  
     
     
         32 . The fuse of  claim 27 , wherein said central region is narrower than each of said two terminals.  
     
     
         33 . The fuse of  claim 27 , wherein said central region has a smaller volume of conductive material than either of said two terminals.  
     
     
         34 . The fuse of  claim 27 , wherein said central region has a smaller cross-sectional area taken transverse to a length of the fuse than a cross-sectional area of each of said two terminals taken transverse to the length of the fuse.  
     
     
         35 . The fuse of  claim 27 , wherein said central region is thinner than either of said two terminals.  
     
     
         36 . A semiconductor device structure, comprising: 
 a semiconductor substrate; and    a fuse formed over said semiconductor substrate and including: 
 a first layer comprising a first conductive material; and  
 a second layer comprising a second conductive material, said first and second layers together forming spaced-apart terminals, said first layer forming a conductive link between said spaced-apart terminals.  
   
     
     
         37 . The semiconductor device structure of  claim 36 , wherein said conductive link has a smaller volume of conductive material than any of said spaced-apart terminals.  
     
     
         38 . The semiconductor device structure of  claim 36 , wherein said conductive link is narrower than any of said spaced-apart terminals.  
     
     
         39 . The semiconductor device structure of  claim 36 , wherein said conductive link has a smaller cross-sectional area taken transverse to a length of said fuse than a cross-sectional area of each of said spaced-apart terminals taken transverse to said length of said fuse.  
     
     
         40 . The semiconductor device structure of  claim 36 , wherein said conductive link is thinner than each of said spaced-apart terminals.  
     
     
         41 . The semiconductor device structure of  claim 36 , wherein said first conductive material comprises polysilicon.  
     
     
         42 . The semiconductor device structure of  claim 41 , wherein said first conductive material further comprises at least one of an N-type conductivity dopant and a P-type conductivity dopant.  
     
     
         43 . The semiconductor device structure of  claim 41 , wherein said second conductive material comprises at least one of a metal suicide, a polycide, and a metal.  
     
     
         44 . The semiconductor device structure of  claim 41 , wherein said second conductive material comprises tungsten or tungsten silicide.  
     
     
         45 . A semiconductor device structure, comprising: 
 a semiconductor substrate;    a first material layer formed over said semiconductor substrate and comprising a first conductive material;    a second material layer formed over said first material layer and comprising a second conductive material;    fuse terminals formed by said first and second material layers; and    conductive links formed by said first material layer, each conductive link being positioned between and in contact with at least two of said fuse terminals.    
     
     
         46 . The semiconductor device structure of  claim 45 , wherein said first conductive material comprises polysilicon.  
     
     
         47 . The semiconductor device structure of  claim 46 , wherein said first conductive material further comprises at least one of an N-type conductivity dopant and a P-type conductivity dopant.  
     
     
         48 . The semiconductor device structure of  claim 45 , wherein said second conductive material comprises at least one of a metal silicide, a polycide, a metal, and a conductive alloy.  
     
     
         49 . The semiconductor device structure of  claim 45 , wherein substantially no contact resistance exists between said first material layer and said second material layer.  
     
     
         50 . The semiconductor device structure of  claim 45 , further comprising a dielectric layer disposed beneath at least portions of said first material layer.  
     
     
         51 . The semiconductor device structure of  claim 50 , further comprising a transistor gate conductor formed from at least one of said first conductive material in said first material layer and said second conductive material in said second material layer, said transistor gate conductor being located over said dielectric layer.  
     
     
         52 . The semiconductor device structure of  claim 51 , wherein said transistor gate conductor includes both said first conductive material in said first material layer and said second conductive material in said second material layer.  
     
     
         53 . The semiconductor device structure of  claim 45 , further comprising another structure formed by at least one of said first conductive material in said first material layer and said second conductive material in said second material layer.  
     
     
         54 . A method for fabricating a fuse and another structure of a semiconductor device structure, comprising: 
 forming a dielectric layer over a semiconductor substrate;    forming a first layer comprising a first conductive material over said semiconductor substrate;    forming a second layer comprising a second conductive material over said first layer; and    following said forming said dielectric, first, and second layers, patterning said second layer and said first layer to form the fuse and the another structure.    
     
     
         55 . The method of  claim 54 , wherein said patterning comprises patterning said first and second layers so as to form the fuse and a conductive element of a transistor gate.  
     
     
         56 . The method of  claim 54 , wherein said patterning comprises patterning said first layer so as to form portions of spaced-apart terminals of the fuse and a conductive link connecting said spaced-apart terminals.  
     
     
         57 . The method of  claim 56 , wherein said patterning comprises patterning said first and second layers so as to form additional portions of said spaced-apart terminals without forming a portion of said conductive link.  
     
     
         58 . The method of  claim 54 , wherein said patterning comprises patterning said first layer so as to form spaced-apart terminals of the fuse.  
     
     
         59 . The method of  claim 58 , wherein said patterning comprises patterning said second layer so as to increase a volume of said spaced-apart terminals and to form a conductive link between said spaced-apart terminals.  
     
     
         60 . The method of  claim 54 , wherein said forming said first layer comprises depositing polysilicon over said semiconductor substrate.  
     
     
         61 . The method of  claim 60 , wherein said forming said second layer comprises forming a layer comprising at least one of a metal silicide, a polycide, a metal, and a conductive alloy.  
     
     
         62 . The method of  claim 54 , wherein said forming said second layer comprises forming said second layer having substantially no contact resistance with said first layer.  
     
     
         63 . A method for forming a fuse comprising a link between two terminals, said method comprising: 
 providing polysilicon and metal over said polysilicon;    patterning said link, comprising etching a portion of said metal located next to a site for said link;    patterning said link and said two terminals, comprising: 
 etching a portion of said polysilicon located next to sites for said terminals and next to said site for said link; and  
 etching a portion of said metal located next to said sites for said terminals.  
   
     
     
         64 . The method of  claim 63 , wherein said act of patterning said link occurs before said act of patterning said link and said two terminals.  
     
     
         65 . The method of  claim 63 , wherein said act of patterning said link occurs after said act of patterning said fuse link and said two terminals.  
     
     
         66 . The method of  claim 63 , wherein said act of providing comprises: 
 depositing said polysilicon over a support surface; and    deposting said metal over said polysilicon.    
     
     
         67 . A method for forming a fuse, comprising: 
 forming a layer comprising polysilicon;    forming another layer comprising conductive material over said layer comprising polysilicon;    removing conductive material of said another layer at a region to be located over a conductive link of the fuse; and    removing material of said layer and said another layer to define said conductive link and terminals positioned at different sides of said conductive link.    
     
     
         68 . The method of  claim 67 , wherein said removing material of said layer and said another layer is effected after said removing conductive material.  
     
     
         69 . The method of  claim 67 , wherein said removing material of said layer and said another layer is effected before said removing conductive material.  
     
     
         70 . The method of  claim 67 , wherein said forming said another layer comprises forming said another layer to include a metal.  
     
     
         71 . The method of  claim 67 , wherein said forming said another layer comprises forming said another layer to include a metal silicide.  
     
     
         72 . The method of  claim 71 , wherein said forming said another layer comprises depositing said metal silicide.  
     
     
         73 . The method of  claim 71 , wherein said forming said another layer comprises: 
 depositing a layer comprising metal; and    annealing metal of said layer comprising metal to polysilicon of said layer comprising polysilicon.